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Springsoft delivers unique automation technologies that save time at key pain points in the design and verification of complex digital, analog and mixed-signal ICs, ASICs, microprocessors, and SoCs. Our solutions automate tedious, time-consuming tasks allowing you to spend more time adding value to your designs. Our two product lines are comprised of the Novas™ Verification Enhancement Solutions and Laker™ Custom IC Design Solutions. |
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Novas Verification Enhancement Solutions |
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Our verification enhancement solutions include the Verdi™ Automated Debug System and the Siloti™ Visibility Automation system. |
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Verdi
Automated Debug Solution  |
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Cuts Debug Time in Half
The Verdi Automated Debug System is an advanced solution for debugging your digital designs that cuts debug time by as much as 50%. The debug system: |
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Automates tracing from effects to causes with its unique behavior analysis technology |
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Unifies design comprehension across the following: |
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Abstraction levels |
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- System, Testbench, RTL, Gate |
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Languages |
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- Verilog, VHDL, SV, SVA, SVTB |
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Dynamic and static verification |
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The Verdi system provides additional support for verification and analysis at the implementation level with the nAnalyzer Design Implementation Analysis module. The nAnalyzer module provides a single environment for analyzing troublesome design errors related to clocks, clock trees, and timing.” |
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Siloti Visibility Automation Solution |
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Eliminates Simulation Overhead
The Siloti family of Visibility Automation products transforms verification methodologies by eliminating the overhead associated with dumping data for all the signals in a design. Siloti technology provides full visibility of internal signals for complex IC and system-on-chip (SoC) designs by identifying the minimal set of signals for dumping, generating "on-demand" the rest of the signal data, and correlating gate-level results to the register transfer level (RTL) source code. Siloti products are used during full-chip simulation, emulation and first-silicon prototyping to: |
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Achieve full visibility with minimal impact on verification overhead using the Siloti on-demand data expansion engine |
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Remove the guesswork of what signals to record with the Siloti essential signal analysis engine |
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Slash file sizes, file transfer times and storage costs |
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| LakerTM Custom IC Design Solutions |
| The Laker line of Custom IC Design Solutions includes the Laker Custom Layout Automation System, the Laker Analog Design Platform, the Laker Automated Test Chip Development Platform, and the Laker Flat Panel Display Editor. |
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Laker Custom Layout System |
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Superior Layout Results with Less Effort
The Laker Custom Layout Automation System is a powerful solution for analog, mixed-signal, memory, and custom digital IC design.
The Laker Custom Layout advantage: |
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Patented Magic Cell™ technology |
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- Automates device generation, editing, and manipulation |
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- Dramatically reduces PCell scripting effort |
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Schematic-driven flow and rule-driven automation |
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- Accelerates layout |
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- Preserve hand-crafted quality |
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- Reduce LVS/DRC verification time |
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Design-driven layout technology |
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- Extracts and honors constraints |
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- Automates custom placement & routing for better results faster |
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Laker Advanced Design Platform |
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Open Schematic Editing, Simulation & Debug Environment
The Laker Analog Design Platform (ADP) provides a user-friendly environment for custom design, including schematic entry, simulation console, and waveform analyzer. It is tightly integrated with the most popular analog simulators to provide a complete solution for the rapid design of analog, mixed-signal, memory, and custom digital circuits.
The Laker ADP advantage: |
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Patented schematic generation technology |
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- Generates readable, editable schematics from legacy netlists |
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- Eases browsing of hierarchy and connectivity |
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Integration with all major analog simulators |
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- Simplifies interactive simulation control and waveform analysis |
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Easy-to-use, intuitive schematic-entry |
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- Provides powerful property query and editing functions |
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Laker Automated Test Chip Development Platform
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High Quality Test Chip Layout with Less Effort
The only layout solution dedicated to test chip development, the Laker Automated Test Chip Development Platform removes tedious and error-prone tasks from the test chip development flow. Its advanced automation techniques and an intuitive user interface for creation of reusable parameterized test structures and test line libraries help users efficiently generate test chips without loss of quality or flexibility.
The Laker Automated Test Chip Development Platform advantage: |
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Reduces test chip development cycle time from months to days or weeks |
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Reduces process development costs with fewer mask and wafer re-spins |
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Increases quality of results with easy-to-adjust parameters to optimize process characterization |
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Laker Flat Panel Display Editor
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High Quality Flat Panel Layout Results with Less Effort
The Laker Flat Panel Display Editor is the technology leader in flat panel display physical design. Used by four out of the five top flat panel display manufacturers, the Laker Flat Panel Display Editor has built-in functions tailored specifically to flat panel design and provides unique editing functions that help layout engineers create, manipulate, and verify a flat panel layout in much less time than other solutions.
The Laker Flat Panel Display Editor advantage: |
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Fast pixel creation and editing via a parameterized user-defined device |
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Hierarchical cell placement and extraction |
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Equal resistance wire routing |
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Open and short checking |
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Resistance calculation and cross-probing |
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Flexible polygon text creation |
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Tel +886-3-5794567
Fax +886-3-5799000
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