| Springsoft and our global
network member companies, Novas Software, Inc. and Silicon Canvas,
Inc., have teamed up to form a world-wide product development
and sales network that delivers a wide range of EDA solutions
from IC verification and debug to custom IC design and layout. |
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Verification Enhancement
Solutions  |
| Our verification enhancement
solutions include the VerdiTM Automated Debug System
and the SilotiTM Visibility Enhancement system. Both
Verdi and Siloti are co-developed by Springsoft and Novas and
marketed and sold under the Novas brand. |
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VerdiTM
Automated Debug Solution |
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The Verdi Automated Debug System
is an advanced solution for debugging your digital designs
that cuts debug time by as much as 50%. Verdi provides
powerful technology to help you: |
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Comprehend complex and unfamiliar
design behavior |
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Automate difficult and tedious
debug processes |
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Unify diverse and complicated
design environments |
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| Verdi's capabilities are extended
with additional modules that support verification and
analysis throughout the design flow. Extensions to Verdi
include: |
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nTX
- Enables extensive transaction-level capabilities
for debug and analysis at higher levels of abstraction |
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nAnalyzer
- Provides a single environment for analyzing design
errors at the implementation level, with focus on
issues related to clocks, clock trees, and timing |
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SilotiTM Visibility
Enhancement Solution |
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The Siloti family of Visibility
Enhancement (VE) products transforms verification methodologies
by eliminating the overhead associated with dumping data
for all the signals in a design. Siloti technology provides
full visibility of internal signals for complex IC and
system-on-chip (SoC) designs by identifying the minimal
set of signals for dumping, generating "on-demand"
the rest of the signal data, and correlating gate-level
results to the register transfer level (RTL) source code.
Siloti products are used during full-chip simulation,
emulation and first-silicon prototyping to: |
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Achieve full visibility into the functional operation
of designs with limited impact on verification performance |
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Enable the analysis and debug of gate-level verification
results on the RTL design; and thus |
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Reduce overall verification time and cost |
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| Custom IC Design
and Layout Solutions |
| Our Custom IC design and
Layout solutions include the Laker Custom Design and Layout
System and the Laker-T1 Test Chip Development Platform. Both
the Laker Custom Design and Layout System and Laker-T1 Test
Chip Development Platform are marketed and sold under the Silicon
Canvas brand. |
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Custom Design
and Layout |
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The Laker Custom Design and Layout
System provides a powerful analog and mixed-signal IC
design solution for building designs. It can generate
readable schematics for legacy netlists for design understanding
and reuse. With its patented Magic Cell, rule-driven editing,
built-in router, schematic driven and design driven flow,
the system combines flexibility and controllability along
with intelligent automation to make layout creation and
editing up to 8 times faster than traditional tools with
handcrafted layout quality. |
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Test Chip Development
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Laker T1 is the only available
platform dedicated to test vehicle development. It provides
the easiest user interface to create reusable parameterized
test structures and test line libraries. Conventional
test chip development methods are tedious and error-prone.
Laker T1 delivers automation and efficiency for developing
test chips without losing quality and flexibility. Laker
T1 technology provides |
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More than a 10x gain in test chip development
productivity |
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Savings of millions of dollars in mask-set and
wafer respins caused by human error |
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Easy to implement last minute changes |
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Tel +886-3-5794567
Fax +886-3-5799000
e-Mail 
