SpringSoft EDA Blog
Select Bit Signal and Display Entire Bus on nWave
March 11, 2010
The Verdi system provides the Add Full Bus command in nWave to automatically add the entire bus when a bit signal is selected. The following steps and figure demonstrates the usage of this command:
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Find Signals with Regular Expression
March 4, 2010
The Verdi system supports searching signals by Regular Expression. This capability provides a flexible way for users to find signals of interest quickly. The following steps provide an example for how to use this capability.
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Convert the Laker system’s Layout Window to a White Background
February 25, 2010
On occasions where the default black background is too dark, it is possible to change to a white background color. To do this, follow these steps: 1. Find your Laker install directory. For example: /tools/laker. 2. Under the subdirectory: etc/, find the file: leoDsgWnd.fm.
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A Unified FSDB Dumper for Cadence IUS, Synopsys VCS and Mentor Graphics ModelSim Simulators
February 18, 2010
A new breed of FSDB dumper is provided since Novas 2009.10. Different from previous FSDB dumpers, the new dumper is unified to support a broader range of simulators and versions. Currently, the new dumper can support Cadence IUS 6.2, Synopsys VCS 2006.06, Mentor Graphics ModelSim 6.4b and their later versions.
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Enhanced On-Demand Assertion Debugging Methodology
January 18, 2010
Assertion-based Verification (ABV) is now a widely used methodology to monitor whether the design's behavior meets the specification intent. For a big design, there may be a dozen or even hundreds of assertions in the design and, as is increasingly more common, the assertions may be spread all over the design hierarchy. Managing assertions, visualizing results, and debugging assertions becomes a big issue in this type of environment.
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