SpringSoft EDA Solutions Blog
SpringSoft EDA Solutions Blog
Welcome to the SpringSoft EDA Solutions Blog.
The EDA blog is intended to provide users insights on how to use SpringSoft’s solutions more effectively. From time to time we’ll also post material related to user experiences. We welcome your feedback and input on the EDA blog posts, so please don’t be shy if you have questions or comments.
ADP Hierarchy Editor
April 5, 2011
The Hierarchy Editor window has been introduced in the Laker™ Advanced Design Platform (ADP) to allow easy switching among view types for netlists. Users can create the configuration to specify the binding view for each cell/instance and then...
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Use Batch Mode Behavior Analysis (BACOM) to Reduce Time to Bring Up Siloti Session
March 29, 2011
The Siloti™ Visibility Automation System (part of the Novas Verification Enhancement Solutions) needs to perform Behavior Analysis on the related design scopes when the Data Expansion command is used for the first time. When this happens,
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Fault Dropping Improves Certitude™ Efficiency & Quality of Results
March 22, 2011
One important goal of the Certitude development team is to continually improve the quality of the results presented to the user for analysis. By quality, we mean relevance to “big problems” in the user’s verification environment and uniqueness –
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Visualize Power Intent in Schematic View
March 10, 2011
The Power Map window can validate whether all signals between power domains are guarded with isolation rules if a possibility exists that the domain a signal is coming from (‘from’ domain) is off while the domain the signal is going to (‘to’ domain) is not.
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Digital Implementation in the Laker Custom Environment
March 1, 2011
Chances are, if you are the one doing the digital blocks in a “big A , little D” (primarily Analog) environment, you are either handcrafting the digital design from a schematic, or – for larger blocks – sending it out to a megabucks digital place and route tool, and then modifying it afterwards.
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Conditional Alias for Viewing Waveforms
February 17, 2011
The waveform view (nWave window) in the Verdi™ Automated Debug System provides the capability to attach an alias to the waveform value which gives a better way to visualize the waveform. Now the capability has been further improved for adding conditions, so that the tool can...
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The New Laker ADP Simulation Console
February 10, 2011
The Laker™ Advanced Design Platform (ADP) unites the full-featured Laker schematic editor, open Simulation Console and LakerWave™ waveform analyzer to create a complete circuit design environment. It works seamlessly with SpringSoft’s award-winning Laker Custom IC Layout system...
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Batch Mode Utility to Extract Clock Trees: nClockTree
February 2, 2011
The Verdi™ Automated Debug System with the nAnalyzer™ Design Analysis module provides full functions for extracting clock trees and qualifying CTS (Clock Tree Synthesis) settings. However, the clock tree extraction has to be processed...
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Certitude™ Non-Detected Faults: Results Analysis Considerations
December 7, 2010
If you are a Certitude user, you know that non-detected (ND) faults are the typical starting points for the results analysis process. An ND fault indicates that Certitude has propagated the effect (incorrect operation) of an injected fault to the boundary (outputs) of the design, but the verification environment (VE)...
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Power-aware Debug for Gate Level Designs
November 30, 2010
When the RTL design is converted to a gate-level design, part of the power intent defined in CPF(CommonPower Format )/UPF(UPF - the IEEE 1801-2009 standard) power files is 'synthesized' either by a synthesis tool or by the designers manually.
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