MemoryCanvas™ – A Memory Instance and Compiler Automation Tool
Using the powerful database and GUI of the Laker Custom Layout Automation System, Spectral Design and Test Inc has created a new software application called MemoryCanvas that eliminates the need to write code to implement a memory compiler or a complex memory instance. MemoryCanvas uses a unique approach involving the definition of a graphical floorplan to convey assembly instructions. Any memory type from SRAM, ROM, CAM, Cache or FLASH can be defined in MemoryCanvas. It provides complete assembly and netlist generation and incorporates full compiler parameterization as needed. The efficient Laker database enables MemoryCanvas to produce a fully expanded schematic of memory instances. These schematics are functional for netlist generation and are used in LVS and simulation as well as providing useful guidance to layout designers to see signal flow and leaf cell adjacencies at the schematic level. Other commercial compiler tool offerings do not support this capability. The floorplan and full schematic instances also serve to document the design and compiler together in one context.
Sample
MemoryCanvas floorplan showing floorplan blocks with associated leaf cells
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Complex patterns such as binary counts for decoders are simple to specify in MemoryCanvas |
The layout view is driven graphically from the schematic floorplan as well. This ensures a tight coupling between design and layout teams. This method of defining the assembly essentially ensures a correct-by-construction result between schematic and layout. MemoryCanvas implements a schematic driven layout methodology at the memory macro level.
Fully functional hierarchical Instance schematic |
MemoryCanvas provides critical netlists used for Memory characterization and timing view generation. It supports automatic creation of “donut” or “ringed” arrays that can be used to reduce the device count significantly for timing verification or characterization. It also supports the automatic reduction of Pi -networks to even more dramatically reduce the device count for efficient and accurate timing and power simulations. There are several controls for users to define the paths that are selected as critical for simulations and yet minimimizes netlist size.
Support and maintenance of memories becomes much easier using MemoryCanvas as the graphical nature of the tool provides immediate feedback to developers about how the memory is constructed and what the design dependencies are. MemoryCanvas floorplans are fully process-independent such that migration of a memory to a new process will not incur any additional effort for assembly.
Using the powerful database and rich interface feature set provided by the Laker Custom Layout Automation System, it was very straightforward to implement the highly productive user paradigm employed in MemoryCanvas.
For more information about MemoryCanvas or Spectral Design and Test Inc., contact: sales@spectral-dt.com or visit the Spectral website at www.spectral-dt.com
