Verdi System Deployed by TAEC Design and Verification Teams to Accelerate Debug of Custom SoC and ASIC Solutions

SAN JOSE, Calif., August 1, 2005 - Novas Software, Inc., the leader in debug systems for complex chip designs, today announced that Toshiba America Electronic Components, Inc. (TAEC) has adopted Novas VerdiÔ Automated Debug System as its debug platform. The Verdi system will be used across internal design teams and in TAEC SoC Design Centers to accelerate functional verification and realize time-to-market goals for custom system-on-chip (SoC) and ASIC designs.

TAEC has been using Novas debug products for several years, first with the DebussyÒ Debug System. Novas second-generation Verdi debug system is being deployed as an integral part of TAECs custom chip, soft intellectual property (IP) platform approach to SoC design to support its internal design team and customers. TAECs complete business solutions mitigate design risk and ensure high-yield manufacturing of custom SoCs and ASICs for the computing, wireless, networking, automotive and digital consumer markets.

"Our teams work on extremely complex designs with advanced process technologies, often involving very large gate counts and significant amounts of third-party IP. These factors increase the magnitude of the verification challenge and impose additional time and cost constraints on our engineering efforts," said Shigenori Imazato, vice president of engineering at TAECs SoC Design Centers.   "With the Verdi system, we are able to implement a much more effective, automated debug methodology for finding problems faster and earlier in the development cycle."

"The growing demand for custom SoC solutions means TAEC design teams are in a constant race against time to cut design cycles and quickly ramp up to high-yield production volumes," said Scott Sandler, president and CEO of Novas.  "Were pleased that TAEC has adopted Verdis powerful approach to debug that gives engineers more visibility into their designs and improves overall verification productivity."

Verdi is a complete mixed-language debug system that automates the process of understanding how complex IC and SoC designs work or why they do not.  It provides a universal debug platform and common interface for accessing all the design knowledge and analysis engines needed throughout the verification tool and methodology flow. Engineers can analyze cause-and-effect relationships and visualize design behavior over time to better understand and accelerate debug of third-party intellectual property, legacy design code and new or unfamiliar components.