Topic: Design Challenges and Opportunities for EDA Vendors on Developing Leading Edge Wireless & Handheld Consumer Products

As foundries continue to enlarge design capacity by qualifying new nodes (65nm/55nm, 45nm/40nm, 32nm/28nm) every two years, and semiconductor system companies have a golden opportunity to compete in the growing wireless and handheld consumer markets. What are the business drivers, product requirements, and design / test challenges? What are the opportunities for EDA partners to enable and contribute? How an EDA company stays competitive and profitable? What would be the right partnership across design, EDA, IP, ATE, foundry, SAT, and university to move the innovation and economic value chain much quicker?

In this talk, Dr. Chen will share his perspective from both engineering and business points of views. The goal is to identify requirements, challenges, and opportunities driven from a product concept to high volume silicon. Then stimulates discussion for semiconductor & EDA partners to collaborate.

Topic: Enhancing the PLL Performance by DSP techniques – A Monolithic Low-Bandwidth Jitter-Cleaning PLL with Hitless Switching for SONET/SDH Clock Generation

The CMOS technology scaling in recent years revolutionizes the traditional analog IC implementation by partitioning more analog-intensive/sensitive components into the digital domain. The result is a more compact solution yet without compromising the system performance. Demonstrated in this talk, in the SONET (Synchronized Optical Network) system, the integer-N clock synthesizer was traditionally implemented by the external PLL/FPGA combo with discrete VCXO. The discrete module is costly, bulky, and susceptible to the environmental noise coupling. The proposed solution integrated the on-chip low-bandwidth (< 1KHz) DSP loop filter and the 20-bit digitally-controlled LC-VCO. The chip sits on an 11x11 Ceramic BGA, supporting frequency translations from 19.44MHz to multiple OC rate. With output rate 622.08MHz, the spot phase noise at 1MHz offset is as low as -145dBc/Hz. With the help of sigma-delta ADC, the phase information is digitally manipulated to enable the hitless-switching. This work was presented in ISSCC2006 (session 13.3)

Topic: Handle the Complexity with Higher Abstraction Level Modeling: A SoC Platform Design Practice

ESL design methodology is a hot topic recently. In this presentation, a SystemC virtual platform based on middle-out or meet-in-the-middle philosophy is proposed. Furthermore, an ESL design flow linked from SystemC virtual platform, RTL platform, FPGA to chip is proposed as well.

Topic: Challenges for custom layout at nanometer process

When IC designs move down to nanometer process nodes to pack more functionalities onto a single chip, designers are facing ever increasing number and complexity of design rules and also need to cope with DFM issues. The shape-based routing lends itself well to assimilating nanometer design rules and constraints found in custom layout and performing optimizations locally to improve yield.

Topic: FPGA prototyping system verification trends & Challenges

To evolving technology in ASIC and/or SOC design is compelling participant to improve methodologies and tool flows to gain a firm foundation in this highly competitive business. Today FPGA chip performance is getting higher and also the FPGA capacity is getting bigger. Current FPGA features open a new space for the verification methodology. With increasing design complexity, popularity of the low power design, and very high speed serial I/O interface, FPGA prototyping system user still facing a lot of challenges. In this session, I like to address some possibility method to overcome these issues.

Topic: Is Multi-Thousand-Core Processor Foreseeable?

近年來，多核心架構成為處理器大廠和研究單位著力甚深的領域。隨著商用雙核、四核等多核心處理器與其系統產品陸續面世，學術界與產業界亦有數百核心處理器之研發工作，未來若要開發出擁有數千個核心的處理器，所牽涉的技術問題絕不僅止於硬體層次之整合，Electronic Design Automation (EDA)設計工具與應用軟體等將扮演關鍵角色。