Power-Aware Debug Challenges & Technologies
Power has emerged as a major concern in IC design. Emerging power format standards allow one power definition to be used throughout design, verification and implementation. But they also increase complexity in verification and debugging. Although the complexity of designs increases when power requirements are specified using the new CPF and UPF standards, debug automation techniques are advancing to help engineers keep ahead of the comprehension curve. Putting the visualization and tracing of these formats on the same plane with HDLs is the foundation and the minimum requirement for productive debug automation for power-aware designs.
This seminar will discuss the debug challenges associated with power management and the advanced technologies that will address them.
Join us on Wednseday, July 29th @ 2PM
