Verification Enhancement Solutions
The Verdi Debug System has been the premier debug solution for gate and RTL verification and this technological leadership is now further enhanced with new support and capabilities in the areas of testbench and power-aware debugging, which will showcased at DAC in 2009.
For large RTL and gate level environments, the Siloti Visibility Automation System provides dramatic reduction in simulation run-time and size of dump files with no loss in visibility. At DAC, the Siloti system's new simpler use-model that allows seamless use with Verdi will be introduced.
In March, SpringSoft completed the acquisition of Certess, and has fully incorporated the Certitude Functional Qualification System into its product line. At DAC, this new way to obtain an objective measure of the quality of verification environments will be highlighted.
Power Aware Debug and Analysis
As end-applications have demanded optimized power usage, especially in mobile devices, engineers have been forced to consider power much earlier in the design cycle. In particular, power intent in the form of standard CPF (Common Power Format) and UPF (Unified Power Format) can be specified early and utilized throughout the design and verification flow. For verification, designs can now be simulated more realistically with power intent considered by the simulation engine. This has great benefits, but there is an additional burden during debug, as engineers must perform root cause analysis with power intent considered ("is that X due to functional problem or a power problem?"). At DAC 2009, we will highlight the Verdi system's new Power Aware debug capabilities with support for both UPF and CPF formats.
Testbench Debug and Analysis
The ever-increasing adoption of SystemVerilog as a verification language adds new requirements for debug and analysis. The language is object-oriented and this has driven the emergence of methodologies and standard class libraries that automate common verification tasks and encourage best practices. This has helped users to easily create realistic multiple scenarios to stimulate and monitor the DUV. The Verdi Debug System's new and unique structured message-based debug technology includes testbench logging and integrated interactive debug. At DAC, we will highlight recent enhancements in this area and a methodology to log all transactions from VMM or OVM-based testbenches into the standard FSDB format. This in turn can drive new UML-inspired views such as a sequence diagram view.
Simulation Runtime Reduction and File Size Optimization
Siloti is the only solution geared to reducing simulation run-time and the size of trace files that are necessary for debug and analysis. It speeds up simulation, cuts storage requirements, and in some cases provides visibility for simulation runs where a full dump was simply not feasible. At DAC 2009, we will highlighting a newly refined use model that makes Siloti more natural and seamless for Verdi users. With this new use-model, it becomes straight-forward for all users to adopt Siloti and take advantage of its benefits.
Functional Qualification
Today's leading-edge designs are verified by sophisticated and diverse verification environments, the complexity of which often rivals or exceeds that of the design itself. Despite advancements in the area of stimulus generation and coverage, existing tools provide no comprehensive, objective measurement of the quality of your verification environment. They do not tell you "how good" your testbench is at propagating the effects of bugs to observable outputs or detecting the presence of bugs. The result is that decisions about when you are "done" verifying are often based on partial data or "gut feel" assessments. The CertitudeTM Functional Qualification System is the first EDA solution to provide an objective measure of the quality of your verification environment and guidance on how to improve it. Certitude injects potential bugs into your design and evaluates the ability of your verification environment to catch them. It completely analyzes whether the potential bugs are activated, propagated to observable outputs, and detected, thus identifying whether you need to add more tests or checkers. The result is higher confidence in your verification results. At DAC, we will show how Certitude integrates easily with your existing simulation environment and applies these patented techniques to provide comprehensive, objective feedback on the quality of your verification environment and how to improve it.
