SpringSoft Seminars @ DAC
Come by booth #1357 to attend the following Seminars:
- Getting You Closer to Verification Closure: Techniques for Assessing and Improving Your Verification Environment
- Monday, June 14 @ 2:30PM
- Tuesday, June 15 @ 4PM
- Laker Custom Digital Place & Route Breathes Life into Custom Digital Design
- Tuesday, June 15 @ 1:30PM
- Memory Canvas: A New Graphical Tiling Engine for Embedded Memory Generation
- Tuesday, June 15 @ 10:30AM
GETTING YOU CLOSER TO VERIFICATION CLOSURE: Techniques for Assessing and Improving Your Verification Environment
By George Bakewell, Director, Product Marketing for Functional Qualification, SpringSoft
Today's leading-edge designs are verified by sophisticated and diverse verification environments, the complexity of which often rivals or exceeds that of the design itself. Despite advancements in the area of stimulus generation and coverage, existing techniques provide no comprehensive, objective measurement of the quality of your verification environment. They do not tell you how good your testbench is at propagating the effects of bugs to observable outputs or detecting the presence of bugs. The result is that decisions about when you are "done" verifying are often based on partial data or "gut feel" assessments. These shortcomings have led to the development of a new approach, known as Functional Qualification, which provides an objective measure of the quality of your verification environment and guidance on how to improve it.
This seminar provides background information on mutation-based techniques - the technology behind Functional Qualification - and how they are applied to assess the quality of your verification environment. We'll discuss the problems and weaknesses that Functional Qualification exposes and how they translate into fixes and improvements that give you more confidence in the effectiveness of your verification efforts. We'll also review recent technical advances that enable usage earlier in the verification process, when results can provide critical guidance on the deployment of precious verification resources. Finally, we'll show a brief demonstration of the CertitudeTM system, the industry's first Functional Qualification solution.
Laker Custom Digital Place & Route Breathes Life into Custom Digital Design
By Hung-shih Wang, Technical Marketing Manager, SpringSoft
SpringSoft's new custom digital place and route solutions bring new levels of efficiency to digital layout in a mixed-signal design. The LakerTM Custom Row Placer and Laker Custom Digital Router save you time with unique automation technologies for placement and routing of cells for digital blocks within the Laker Custom Layout System.
In this seminar, we will show you how the Laker Custom Row Placer and Laker Custom Digital Router, combined with the flexibility and ease-of use that the Laker layout system is known for, work together to create the most productive custom digital design environment available today.
Both the Laker digital router and digital row placer work seamlessly within the Laker Custom Layout Automation System so that design - even a full-custom mixed signal design - can be done in a single environment for even greater time savings. Adjust the aspect ratio or block shape automatically; manually move, swap and edit individual cells; or manually route critical nets and complete routing with the Custom Digital Router. Working in a unified environment removes the need for the design to move between layout and Automatic Place and Route (APR) tools, we will show you how you can achieve results that are comparable to full-custom layout for custom digital blocks that might otherwise be too large, or too time-consuming to do by hand.
Memory Canvas: A New Graphical Tiling Engine for Embedded Memory Generation - Leave The Code Behind!
By Deepak Mehta & Bill Palumbo, Principals of Spectral Design and Test
Introducing a new way to define memory compilers and complex memory instances. No programming required!! Memory CanvasTM simplifies the task of defining complex memory instance generation and memory compiler definition. Using only an intuitive graphical floor plan with textual annotations, designers can now easily define the assembly of Embedded Memories. Using a correct-by-construction methodology, the time needed to define, implement, debug and document memory compilers can be cut from weeks to days. You are invited to come and see a live demo of how a complex Content Addressable Memory is built!
