The EDA community has struggled with false starts in the area of custom IC design automation. Too much has been promised and too little delivered, leading to a lack of trust by designers who are inherently skeptical of tools that purport to do “automagically” the tasks that they have perfected over years or decades of experience.

 

After all, the people who put together custom IC layouts are the true craftsmen and women of electronic design. What they do is more like art than it is like electrical engineering, and is not so easily captured in algorithms. But like so much else in chip design, as semiconductor technology progresses and yesterday’s chips become today’s blocks, complexity and the sheer magnitude of the problem cause even the most committed manual designers to look carefully at automation options.

 

The inflection point for the adoption of custom IC design automation seems to be the 90nm process technology. Automation for designs at advanced process nodes has become practical as technologies such as the shape-based routing in Pulsic’s UniRoute, the built-in design rule engine in Ciranova’s PyCells, and the MCell parameterized devices in SpringSoft’s Laker custom IC layout system have emerged and matured.

 

As users have deployed these tools, they have built confidence in their ability to get results that are at least as good as their hand-crafted designs, with much less effort. Meanwhile, transistor-level floorplanning has become well accepted, and custom digital design has gone through a transformation.

 

Not so long ago custom digital designs (processors, memories, FPGA fabrics, flat-panel displays) were fully handcrafted at the transistor level. More recently, designers began using standard cells, but placing and routing them by hand. And now we’re seeing a shift to a hybrid of hand and automated placement and routing of standard cells for these types of designs.

 

SpringSoft’s view is that adoption of custom IC design automation will accelerate rapidly, driven not only by necessity born of complexity, but also by increasing practicality due to “modular” innovation and open interoperability. One of the problems faced by earlier practitioners of custom IC design automation was that they had to build the whole flow. There were no standards for interoperability.

 

Today, however, the maturing of the OpenAccess standard makes it possible for EDA vendors to focus on automating a particular part of the flow, and for users to adopt the best automation technologies from a variety of sources and weave together a custom IC flow using best-in-class tools. Great examples of the collaboration that OA makes possible are the IPL Alliance, which is making possible open Process Design Kits, and the OpenEngines initiative, an emerging alliance of end-user companies such as Sun, Intel, and AMD that aims to create an open environment in which they can combine their own automation innovations with those of EDA vendors and academia to drive custom design automation further.

 

Another problem that befell earlier efforts to automate custom IC design was that they attempted to automate by raising the level of design abstraction before lower-level automation building blocks were in place. Now that transistor-level routing, floorplanning, and custom placement techniques are available and deployed, it may be time to re-address that opportunity. Although much more research and development are required, and no one should lose focus on engine-level improvements, it is more a question of when, not if, higher-level automation will become practical too.