TSMC launches its story for DAC
By Ron Wilson
EDN
Keeping the design community informed on its progress in design support, TSMC this week unveiled its major talking points for DAC. They include a new digital reference design flow that embraces both the use of system-level descriptions and the growing dominance of IP in front-end design, TSMC's first-ever analog/mixed-signal (AMS) reference flow, and an expanded RF reference design kit.
TSMC deputy director of marketing for design services Tom Quan said that this year's Reference Flow-11.0-will incorporate several new features and many enhancements. Chief among the new items is a system-level powr/performance/area (PPA) modeling capability TSMC has been developing. "We've been working with IP providers to get data and run experiments," Quan said. The modeling system will provide an API to system-level virtual platforms from Cadence, Mentor, Synopsys, and Forte Design, allowing those tools to query the TSMC API for a PPA estimate for an IP block in a particular TSMC process. This estimation ability, since it will be based on actual TSMC data developed with the IP providers, should provide a solid grounding in reality for the system-level phase of IP integration.
Continuing the theme of IP integration, the new reference flow will also make room for the Arteris network-on-chip fabric, giving SoC designers a way to generate globally-asynchronous, locally synchronous interconnect to nearly plug together functional IP blocks. Taking the interconnect theme off on another axis, the new flow will also include the beginnings of support for modeling and analysis of through-silicon vias, interposers, and stacked-die packages as part of a single system-in-package design flow.
The second major element in TSMC's DAC message will be the foundry's first AMS reference flow. Quan said the flow was assembled for the 28nm node, but will also apply to 40nm designs. Representing about 50 engineer-years of work in qualifying and building, the flow attempts to anticipate and deal with all of the novel challenges that experienced analog designers will encounter at these aggressive nodes.
The TSMC team used a 28nm, 1.6 GHz PLL as the test vehicle for the flow, Quan said. Key points of departure from conventional AMS design will include a TSMC-designed engine to estimate layout-dependent transistor parameters, called by SpringSoft Laker during layout. A number of small-vendor tools are also included, each aimed at a particular problem area in advanced geometries. These include Ciranova place/route, edXact simulation, Silicon Frontline 3D extraction, and Berkeley Design Automation simulation for IR-drop and electromigration analyses.
Finally, Quan said that TSMC has revised and extended their RF reference design kit. The kit serves multiple purposes: as a genuine reference design for an RFID block, as a reference flow, and as an illustration of best RF design practices for working with the foundry. Enhancements to the flow include substrate noise analysis based on Coupling Wave Solutions; electromagnetic analyses using Helic, Integrand Software, and Lorentz Solution tools; and assisted circuit sizing and design centering employing MunEDA.
Of the three advances, Reference Flow 11.0 is pretty much as expected, the next step in a long line of flow recommendations. But by venturing into the areas of AMS design and especially the more esoteric corners of RF design, TSMC is taking more of a risk. The company is bringing needed foundry data and fabrication experience to the design flow, but they are bringing these benefits to a notably independent, prickly, and often traditional set of designers who may or may not welcome the notion of a reference design, let alone a reference flow. That part will be interesting to watch.
