Laker Custom Layout Automation System

The Laker™ Custom Layout Automation System offers powerful solutions for analog, mixed-signal, memory, and custom digital IC design that address key pain points in the layout process. The Laker layout system provides an intuitive methodology and controllable automation that let you quickly achieve superior layout results. The Laker layout system helps you:

• Simplify your job by automating many tedious and error-prone layout tasks;
• Maximize your layout skills using advanced automation that you control;
• Minimize your CAD support requirements; and
• Reduce your overall cost of design.            

Core Features  |  Advanced Features  | Open System  |  OpenAccess Support  |  Datasheet

Superior Layout with Less Effort
Hundreds of companies have deployed the Laker Custom Layout Automation System in their design flows to produce high-quality, high-density layout of advanced chip designs. Laker automation technologies reduce the effort required to obtain optimal layout by helping you:

• Speed up your project and optimize your layout at the same time;
• Efficiently interact with your netlist, schematic and layout data in a single working environment;
• Cut overall DRC/LVS run times by creating layout that is correct the first time; and
• Reduce or eliminate PCell scripting with unique device generation technologies.

Unique Automation Technology
Magic Cells and built-in DRC engine: At the core of the Laker layout system’s controllable automation is SpringSoft’s patented Magic Cell (MCell™) parameterized device technology and a built-in design rule check (DRC) engine that drives the system’s rule-driven layout capabilities. MCells enable a highly automated schematic-driven layout (SDL) flow that includes the user-controllable device planning, wiring and manipulation capabilities of the Stick Diagram Compiler.

• MCells include transistors, resistors, capacitors, contacts/vias and guard rings
• MCells enable the rapid generation of optimized layout structures for complex devices, such as multiple-gate transistors, guard-rings, contact arrays, inter-digitized resistors and capacitors
• MCells are technology-independent and require no user scripting

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Core Features

The Laker layout system provides rule-driven layout so you can rapidly realize, place, route, and edit physical layout that is DRC and LVS correct. Unique controllable automation simplifies numerous tasks from measurement to device generation. The built-in DRC engine drives the application of design rules through device generation, layout, and routing.

Rule-driven layout: Automatically checks, displays, and snaps to width, space, notch, overlap, and enclosure rules in real time. With the Laker system you can:

• Select an area of layout and automatically correct DRC violations
• Ensure LVS-correct layout results with flight lines that display connectivity information to guide and speed-up wiring operations
• Automatically identify any created shorts in real time
• Move same-layer routes out of the way when you are hand-routing high priority nets with Push Wire feature
• Meet rules for width, space, notch, overlap, and enclosure including foundry-recommended and DFM rules

Built-in Routers: The Laker Custom Layout Automation System’s built-in routers use the design’s connectivity to automatically finish wiring "on the fly." Features include:

• Point-to-point Router that lets you either automatically or interactively create a DRC-correct route between the source and target
• Interactive, DRC-correct Pathfinder that follows the cursor in “point and click” routing mode, recognizing and routing around same layer metal – or you can switch layers with the click of a bind key and Pathfinder will retain connectivity by automatically placing the appropriate via stacks
• Route-by-label function that automatically creates routes between multiple points as guided by text or labels
• Net Router that automatically routes single or multiple nets

User-Defined Device (UDD): For complex devices such as spiral inductors, the Laker layout system offers a convenient tool that lets you create parameterized devices (similar to PCells) without scripting.

• Draw a device in the UDD layout window, set layout rules and parameters using built-in forms, and assign parameters that can be changed by users
• Existing layout including legacy PCell layout can be read into the UDD tool and parameterized for use in the Laker layout system

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Advanced Features

The Laker Custom Layout Automation System uses unique technologies to exploit design rules, connectivity and parameters during layout in an efficient, consistent, and automatic way. The system’s schematic-driven layout (SDL) capabilities save you time so you can focus on creating the best possible layout. By handling dozens of critical requirements in an automated yet natural way, the Laker layout system keeps you in complete control of the quality of your results.

Schematic-driven layout: You are able to rapidly create optimized layout that is DRC/LVS-correct in less time without sacrificing density or design styles. Both netlist and schematic views are included with the world-class Laker layout editor for an intuitive SDL working environment, which includes:

• Hierarchical design browser allows you to rapidly search the hierarchy and cross probe between schematic, netlist, and layout. Modify the design hierarchy for more efficient layout by flattening logical groups of devices into higher level devices
• Schematic view enables schematic-driven layout. Cross-probe with design browser to identify candidates for flattening. Automatically identify repeated patterns, associate optimized layout for those patterns and generate layout in seconds
• Layout editor enables rapid, rule-driven layout. Realize, place, route, and edit physical layout that is DRC- and LVS-correct
• Patented automatic schematic generator creates a readable schematic from EDIF, Verilog®, CDL or SPICE netlists

Stick Diagram Compiler: Based on SpringSoft’s unique MCell technology, the Stick Diagram Compiler executes transistor floor-planning on-the-fly during device generation in the SDL flow. View and optimize device layout at a higher level of abstraction; swap, merge, move, spilt and align gates at a symbolic level without having to worry about design rules, connectivity or parameter values.

• Built-in Automatic Transistor Placer offers a multi-row placement capability for PMOS and NMOS transistors that displays the best transistor placement for area and routing based on your given placement criteria

Design Hierarchy Manipulation for Layout Optimization: Manipulation of circuit hierarchy in the design browser and layout windows drastically reduces the time you spend laying out repeat circuitry.

• Create a pattern by grouping multiple circuit elements into a higher level device for a more efficient layout implementation
• Automatically locate the pattern throughout the circuit, associate all occurrences of it with an optimized layout generated for the pattern, and assign connectivity

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Open System

The Laker Custom Layout Automation System provides unparalleled interoperability and an open environment that enables you to employ best-in-class design tool flows that include analog simulation, physical verification, extraction and much more.  This open system provides:

• Interoperability with layout legacy design tools so that layouts created in those tools can be viewed and edited in the Laker layout system;
• Seamless integration with Calibre® and Hercules™ physical verification tools that help you to execute DRC and LVS from the Laker window and easily browse and debug the results; and
• Complete Tcl support including language syntax and selected extensions to give you maximum flexibility in tool customization, database query, and layout creation.

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OpenAccess Support

SpringSoft also provides a native implementation version of the Laker Custom Layout Automation System on OpenAccess (OA). Benefits of the Laker layout system on the OA interoperability standard include:

• Support for all the necessary formats, libraries and design kits
• Support for all interoperable process design kits (iPDKs) from TSMC
• Interoperability with other EDA tools that support the OA standard

The Laker layout system offers the most robust support for OpenAccess

The Laker layout system is the only solution that supports all three OpenAccess interfaces from Si2.

The Laker Custom Layout Automation System Offers Superior Layout Results with Less Effort

The Laker Custom Layout Automation System offers rule-driven and schematic-driven capabilities for generating full custom layouts in a much shorter time than manual layout methods. Its controllable automation technology simplifies the layout process while reducing verification and debug efforts. The open architecture seamlessly integrates best-in-class third-party tools. More than 300 companies worldwide including cutting-edge IDMs, pure-play foundries, and fabless semiconductor companies have already chosen Laker products to save time without sacrificing quality.  The Laker Custom Layout Automation System is another example of how SpringSoft is accelerating engineers.

Download the datasheet: 

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See Related Technical Articles:

PRODUCT HOW-TO: Using standards-based tools to scale chip designs to next-gen geometries

Deciphering the Analog Automation Code

 

Read Whitepapers about Laker Technology

Controllable Automation and Interoperability Standards
Schematic-Driven Layout Automation
PCell Caching in OpenAccess
Laker PDK
Laker Custom Layout Parameterized Devices
Digital Place & Route in a Custom Design Environment

 

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Product name	License Exception	ECCN NO#	Export Administration Guidelines and Requirements
Laker Custom Layout Automation System	NLR	3D991	General Prohibitions Part 736.2 in the Export Administration Regulations