nAnalyzer Design Analysis

Design Implementation Analysis

The nAnalyzer™ Design Implementation Analysis solution provides you a single system for understanding and debugging critical design implementation issues that typically arise during synthesis and related activities that transform an RTL description into a gate-level netlist that is ready for tapeout.  Throughout the flow, these transformations impact timing closure, power consumption, and clocking schemes.  To detect and resolve detrimental effects in these areas, you must analyze your designs using specialized tools and techniques outside of the traditional simulation flow.  The nAnalyzer solution both augments and enables these analysis steps through the following capabilities:

• Explore, analyze, and identify problems with clock-related logic using powerful clock tree and clock domain extraction and analysis engines
• Identify and isolate potential timing, power, or hot-spot problems early in the process through analysis of the netlist, Standard Delay File (SDF) information, and simulation results
• View, understand, and explore the results of third-party clock, timing, and power analysis tools integrated with the nAnalyzer solution through the Novas Harmony Partner Program.
• Debug and isolate problems identified with the built-in or third-party capabilities using the powerful tracing and exploration features provided in the Verdi™ Automated Debug System

Analyze and debug design implementation issues in a single, comprehensive environment.

Clock Tree and Clock Domain Analysis

Today’s complex designs require special and often sophisticated clock schemes.  Multiple clock domains introduce the need to synchronize data passed between the different domains.  Low-power stipulations require special clock gating techniques.  The integration of third-party IP presents unexpected clock-related challenges at the IP interface.  All of these factors increase the complexity of the clock circuitry and introduce more opportunities for implementation errors and thus incorrect operation.  The nAnalyzer solution provides powerful built-in analysis engines that enable comprehensive exploration and debug of common clock-related issues.

Clock Analysis Features:

• Extract clock trees, clock domains, and clock domain crossings from RTL or gate-level descriptions
• Browse analysis results in text form or display and explore them in intuitive Verdi schematics
• Import SDC information to identify clock sources and further constrain the analysis
• Pre-qualify clock tree synthesis (CTS) scripts to check for incorrect or incomplete constraints
• Develop and export SDC and CTS scripts to drive the CTS process
• Identify common problems such as flops outside of extracted clock trees and clocks connected to non-clock pins
• Verify proper cross-domain synchronization using user-defined synchronization methods
• Import SDF information and/or static timing analysis results to extract and display timing details - level delay, skew, slack time

Timing and Power Analysis

Although dedicated tools exist that provide comprehensive analysis and verification in the timing and power analysis domains, it is often useful to interactively explore timing and power issues outside of these tools.  In some cases, the data required for a comprehensive analysis may not be available.  In other cases, the dedicated tool may take a long time to complete its analysis, but only a quick approximation is needed.  The nAnalyzer solution provides built-in analysis capability in both the timing and power domains to meet these needs.

Timing Analysis Features:

• Import reports from common static timing analysis (STA) tools
• Browse critical path details in text form or display and explore them in intuitive Verdi schematics
• Import SDF information and annotate the delay information on schematic views
• Calculate and display longest/shortest paths based on imported delay information

Power Analysis Features:

• Analyze simulation results and identify areas of heaviest switching activity
• Sort and explore switching activity by signal, module, time, or time window
• Explore related logic using Verdis powerful tracing and visualization capabilities
  
  

Interoperability with Third-Party Tools

Complete analysis and resolution of timing, power and clock scheme related issues often require the application of best-in-class tools dedicated to one of these domains.  The nAnalyzer solution enhances your usability of these dedicated tools by importing, displaying, and enabling the exploration of the analysis results in the familiar Verdi environment.

Supported Tools
Power analysis:

• Sequence PowerTheater

Clock Analysis:

• Mentor 0-in Clock-Domain Crossing
• RealIntent Verix

Timing Analysis:

• Cadence AMBIT
• IBM Einstimer
• Magma Quartz Time
• Synopsys PrimeTime

Summary

The nAnalyzer Design Implementation Analysis solution provides a single environment for understanding and debugging critical design implementation issues throughout the flow.  Powerful built-in engines support the analysis, exploration, and resolution of issues that impact timing closure, power consumption, and clocking schemes.  Support for best-in-class third-party tools enhances the use of these systems and enables results exploration in the intuitive Verdi Automated Debug System.