nECO Automated Netlist Modification

nECO is an integrated graphical netlist modification tool for the Verdi Automated Debug System. The Verdi system accelerates your understanding of complex designs to improve design, verification, and debug productivity. nECO adds the ability for you to isolate logic that needs to be changed in a flattened schematic, make the necessary changes, and write the modified design to a new netlist file.

You may find many reasons to modify the netlist of your complex chip. Often these changes come late in the design process where errors are very costly. Netlist changes are error-prone because the netlist is large, complex, unfamiliar, and hard to understand. Errors such as changing the wrong gate or making a typo are far too common.

nECO improves your ability to make accurate netlist changes by making it easy to understand the necessary change in context. To change a design with nECO, your first isolate the relevant logic using the Verdi system’s standard views and analysis techniques. Then you use a special schematic window in nECO modify the design.

You control how nECO writes the modified design out to a new source code netlist. You can choose to write out the changed files, all logic in the specified hierarchical scope and below, or the entire design. nECO generates a report that details the changes and maintains the original file structure, including white space, so that the old and new files can be easily compared. Comments are automatically placed in the new netlist source files identifying where changes were made.

nECO provides special features for you to manage spare cells. A list of spare cells can be derived from the design via a special naming convention, read from a file, or written to a file.

With the Verdi system and nECO, netlist changes are no longer tedious and error-prone. By locating the logic and isolating it, you can understand exactly what is being changed so verification time and effort are reduced.

Features

• Extends the Verdi system to support netlist-level ECOs (Engineering Change Order).
• Isolates the logic that needs to change.
• Changes the design in the context of the familiar Verdi Automated Debug System.
• Writes a modified design to Verilog netlist with comments.
• Generates reports to track and manage changes in the context of the source code control process.