Simulation is the backbone of functional verification. Use of a testbench to apply stimulus to a design and to check its responses is a long-standing, well-understood, and stable method. The introduction of dedicated hardware verification languages and more recently the integrated SystemVerilog language have dramatically improved the ability to write effective testbenches, improving the overall functional verification process.
However, there are several persistent problems with this approach, mainly: performance, comprehension, and closure. Simulation is never fast enough, especially for large complex designs that require extensive testbenches, which can easily require days - if not weeks - of simulation time for a full run through all the test cases. When the behavior of a design does not meet expectations, or when the expectations are unclear, then engineers face the need to investigate the causes of design behavior by tracing connections within the design in order to comprehend how it works. And even after all this, design teams are left with questions as to whether they have run enough test cases and whether their test environment could detect any and all errors if they were present.
Verification enhancement technologies make it easier for engineers to do more verification in less time, to more easily understand and correct the behavior of their designs, and to improve the quality of their verification environment so they can attain higher levels of confidence in the correctness of their designs. SpringSoft is the only EDA vendor specializing in verification enhancement technologies and solutions. These solutions work side by side with simulators in industry-standard flows using standard languages and interfaces to improve the productivity and quality of the functional verification process.
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