Product Overview

SpringSoft delivers unique automation technologies that save time at key pain points in the design and verification of complex digital, analog and mixed-signal ICs, ASICs, microprocessors, and SoCs. Our solutions automate tedious, time-consuming tasks allowing you to spend more time adding value to your designs. Our two product lines are comprised of the Novas™ Verification Enhancement Solutions and Laker™ Custom IC Design Solutions.

Novas Functional
Closure Solutions

 

Laker Custom IC Design
& Layout Solutions

Debug Automation:
Verdi Automated Debug System
Siloti Visibility Automation Solution

Verification Closure:
Certitude Functional Qualification
Solution

Prototype Debugging:
ProtoLink Probe Visualizer

 

Custom Design & Layout:
Laker Custom Layout System
Laker Row Placer
Laker Digital Router
Laker Advanced Design Platform
Laker Flat Panel Display Editor

Test Chip Development
Laker Automated Test Chip
Development Platform


Verdi Automated Debug System

Cuts Debug Time in Half

The Verdi Automated Debug System is an advanced solution for debugging your digital designs that cuts debug time by as much as 50%. The debug system:

  • Automates tracing from effects to causes with its unique behavior analysis technology
  • Unifies design comprehension across the following:
    • Abstraction levels - System, Testbench, RTL, Gate
    • Languages - Verilog, VHDL, SV, SVA, SVTB
    • Dynamic and static verification

The Verdi system provides additional support for verification and analysis at the implementation level with the nAnalyzer Design Implementation Analysis module. The nAnalyzer™ module provides a single environment for analyzing troublesome design errors related to clocks, clock trees, and timing.

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Siloti Visibility Automation Solution

Eliminates Simulation Overhead

The Siloti family of Visibility Automation products transforms verification methodologies by eliminating the overhead associated with dumping data for all the signals in a design. The Siloti technology provides full visibility of internal signals for complex IC and system-on-chip (SoC) designs by identifying the minimal set of signals for dumping, generating "on-demand" the rest of the signal data, and correlating gate-level results to the register transfer level (RTL) source code. Siloti products are used during full-chip simulation, emulation and first-silicon prototyping to:

  • Achieve full visibility with minimal impact on verification overhead using the Siloti on-demand data expansion engine
  • Remove the guesswork of what signals to record with the Siloti essential signal analysis engine
  • Slash file sizes, file transfer times and storage costs

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Certitude Functional Qualification Solution

Removes Verification Uncertainty

The CertitudeTM Functional Qualification System is the only solution that allows you to evaluate the effectiveness of your verification environment. It does this with unique automation technology that:

  • Objectively measures the quality of the verification environment
  • Identifies verification holes that could hide design bugs

The Certitude system provides detailed information on the activation, propagation and error detection capabilities of verification environments, showing significant weaknesses and bugs that have gone unnoticed by existing tools. The Certitude system answers the question "If there was a bug in your design, could you find it?"

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ProtoLink Probe Visualizer

The ProtoLink Probe Visualizer is an innovative prototype verification solution that dramatically increases design visibility and simplifies debug of off-the-shelf and custom-designed FPGA-based boards.

Probe Visualizer allows you to:

  • Cut prototype debug time in half
  • Improve verification efficiency for early validation of SoC designs
  • Maximize ROI with faster and earlier deployment

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Laker Custom Layout System

Superior Layout Results with Less Effort

The Laker Custom Layout Automation System is a powerful solution for analog, mixed-signal, memory, and custom digital IC design.

The Laker Custom Layout advantage:

  • Patented Magic Celltm technology
    • Automates device generation, editing, and manipulation
    • Dramatically reduces PCell scripting effort
  • Schematic-driven flow and rule-driven automation
    • Accelerates layout
    • Preserves hand-crafted quality
    • Reduces LVS/DRC verification time
  • Design-driven layout technology
    • Extracts and honors constraints
    • Automates custom placement & routing for better results faster

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Laker Advanced Design Platform

Open Schematic Editing, Simulation & Debug Environment

The Laker Advanced Design Platform (ADP) provides a user-friendly environment for custom design, including schematic entry, simulation console, and waveform analyzer. It is tightly integrated with the most popular analog simulators to provide a complete solution for the rapid design of analog, mixed-signal, memory, and custom digital circuits.

The Laker ADP advantage:

  • Patented schematic generation technology
    • Generates readable, editable schematics from legacy netlists
    • Eases browsing of hierarchy and connectivity
  • Integration with all major analog simulators
    • Simplifies interactive simulation control and waveform analysis
  • Easy-to-use, intuitive schematic-entry
    • Provides powerful property query and editing functions

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Laker Automated Test Chip Development Platform

High Quality Test Chip Layout with Less Effort

The only layout solution dedicated to test chip development, the Laker Automated Test Chip Development Platform removes tedious and error-prone tasks from the test chip development flow. Its advanced automation techniques and an intuitive user interface for creation of reusable parameterized test structures and test line libraries help users efficiently generate test chips without loss of quality or flexibility.

The Laker Automated Test Chip Development Platform advantage:

  • Reduces test chip development cycle time from months to days or weeks
  • Reduces process development costs with fewer mask and wafer re-spins
  • Increases quality of results with easy-to-adjust parameters to optimize process characterization

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Laker Flat Panel Display Editor

High Quality Flat Panel Layout Results with Less Effort

The Laker Flat Panel Display Editor is the technology leader in flat panel display physical design. Used by four out of the five top flat panel display manufacturers, the Laker Flat Panel Display Editor has built-in functions tailored specifically to flat panel design and provides unique editing functions that help layout engineers create, manipulate, and verify a flat panel layout in much less time than other solutions.

The Laker Flat Panel Display Editor advantage:

  • Fast pixel creation and editing via a parameterized user-defined device
  • Hierarchical cell placement and extraction
  • Equal resistance wire routing
  • Open and short checking
  • Resistance calculation and cross-probing
  • Flexible polygon text creation

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Laker™ Custom Row Placer

The Laker™ Custom Row Placer provides unique automation for placement of digital custom and standard cells within the Laker Custom Layout environment. It allows precise custom design of the digital blocks often used in mixed signal and custom digital designs in order to meet the critical performance requirements that often times cannot be achieved with a standalone digital automatic place and route (P&R) tool. Its proprietary technology allows you to:

  • Save time with automated creation of digital blocks without leaving the Laker Custom Layout environment
  • Achieve the performance of full-custom layout with the speed of P&R 
  • Enjoy the confidence of using proven standard cells while maintaining hand-crafted quality

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Laker™ Custom Digital Router

The Laker™ Custom Digital Router brings new efficiency to digital design in mixed signal ICs.  When combined with the Laker Custom Row Placer, this new router offers a very effective package for high‐performance digital design in a custom IC layout environment.

The Laker Custom Digital Router saves you time with unique automation technology for routing of digital blocks within the Laker Custom Layout Automation System.  Creating digital blocks within a custom environment allows you to:

  • Avoid time‐consuming switching between digital automatic place and route (P&R) and custom layout environments and the associated data preparation and translation
  • Leverage all the features of the Laker Custom Layout Automation System for things like hand‐routing of critical nets and hand‐optimization of critical cell placements
  • Save time using  proven standard cells for high performance digital applications that previously had to be done by hand

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