Laker Automated Test Chip Development Platform

The Laker™ Automated Test Chip Development Platform saves you time when it matters most. It is a product uniquely focused on test vehicle development, providing an intuitive user interface for creating reusable parameterized test structure and test line libraries. Parameterizing typically hand-drawn structures assigns variables to key drawing dimensions, allowing you to create an almost infinite number of layouts from a single structure. This methodology is particularly applicable for test chips where a large number of devices with very tiny incremental changes need to be generated in order to perform statistically accurate process and electrical analysis. With the Laker Test Chip Development Platform, you are able to change from the tedious and error-prone conventional test chip development flow to an efficient, consistent, and automatic methodology.

Major Benefits

• Reduce test chip development cycle time from months down to days or weeks, accelerating time-to-market schedules for new technology development and the ramp to volume production.
• Reduce process development costs with fewer mask-set and wafer respins by removing the guesswork of manual test chip layout and documentation
• Increase the quality of results with fast and easy adjustment of parameters to optimize process characterization.

Major Features

• Intuitive GUI design flow enables you to create and maintain the parameterized test structure libraries with ease.
• Centralized database lets you manage company-wide test chip assets under one environment.
• Test structure version and privilege control protects your crucial intellectual property.
• Flexible test line templates enable probe card shrinks for process migration.
• Parameterized architecture offers true scalability and reuse across multiple technology nodes.
• Test line routing algorithms deliver custom-tailored test chip routing solutions.
• Automatic document generation in HTML and Microsoft formats.
• Automatic net-list generation enables LVS verification of test lines.

Download Datasheet: Test Chip Development Datasheet