Laker Technology File 

Available Laker Techfile

A Laker™ technology file is an ASCII file presented in Tool Command Language (TCL) syntax. It defines the system unit and the system purpose and layer table required for your layout design.  It also includes several rule definitions for certain design purposes.

At the core of the Laker layout system’s controllable automation is SpringSoft’s patented Magic Cell (MCell™) parameterized device technology and a built-in design rule check (DRC) engine that drives the system’s rule-driven layout capabilities. By working with leading foundries, these features are part of a Laker techfile. Customers are able get the up-to-date tech files directly from the foundry for their applications.

 

The technology files that we provide for foundry service contain 13 sections:

Basic Information defines the title, version and the revision history of the technology file. This section is usually marked by #.
tfLayoutSystemUnit defines all the units required for the system, with the optional display or snap setting.
tfSystemPurpose defines the correspondence between the purpose name and the purpose number.
tfLayoutLayerTable defines the layers that are adopted in the Laker system.
tfStreamIoTable defines the mapping relationship between the internal database and GDSII stream file.
tfLayoutLayerRule defines the rule-driven function that verifies the layout against the design rule.
tfLayoutMagicCell
defines Magic CellTM (MCell) devices. Currently we support core and I/O transistors, contact devices and guard rings for customer applications.
tfLayerConnection defines the connection rule between layers for real-time short detector and hierarchical net tracer, and the layer sequence for path creation.
tfNetRouteRule
defines the rules related to the interactive router for single-layer and the point-to-point router for multilayer routing.
tfAbstractCell defines the abstract rule, including layer definition of pin extraction, rule for blockage generation, and boundary rule.

 

tfAreaEstimation		 defines the equation to calculate the cell boundary of schematic design, such as the width and the length for soft blocks and global pins, and also declares the pin width, pin length, pin space, etc.
tfSubstrateExtraction defines the substrate checking rules and connection rules.
tfDeviceRule declares the measurement rule for gate width and length.

Custom IC Design & Automation

"During custom layout with Laker, we are seeing around 30% productivity increase..."

- Teresa He, vice president of HiSilicon

Custom IC Design & Layout Resources

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