Comprehensive SVTB Debug Capabilities Now Available in the
Verdi Automated Debug System
The Verdi™ Automated Debug System provides a complete debug
solution at the right level of abstraction for understanding
SystemVerilog testbench activity. Verdi’s unique message logging
capability coupled with advanced visualization techniques give you a
thorough picture of your testbench activity and verification
environment. The full-featured interactive simulation control in Verdi
lets you step through complex testbench code for more detailed analysis.
Key SVTB Debug Features Include:
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Full-featured testbench browser that allows you to analyze testbench source code and shows class hierarchy, declarations, and inheritance.
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Unique message-based logging capability that captures testbench behavior.
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Complete integration with traditional HDL dumping for seamless debug.
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Batch mode capability allows you to quickly locate and understand the problem in the testbench code. The batch results can be used as the entry point for interactive debug.
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Unified platform for debugging with multiple languages including a new testbench browser for SystemVerilog testbench code.
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Support for dual-mode debugging that combines analysis of the source code with message and call stack data captured during interactive simulation.
Benefits Include:
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Easily comprehend SVTB activity.
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Quickly traverse inheritance relationships for class and function.
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Customize SVTB-related information into the most popular FSDB waveform format.
