Expand SystemVerilog Implicit Ports in Source Code View

SystemVerilog provides the ability for implicit port connections. Instead of specifying the detailed port connection every time, designers can use “.*” to specify port connections as long as the port name and size matches the connecting net or bus name and size.

The Verdi™ Automated Debug system also provides string support for debugging the SystemVerilog implicit port. If there are implicit ports defines in the source code, a tip window will appear to show the detailed connections when you move the mouse cursor over the “.*”. The following figure shows this capability:

The tip window is just for you to view the connection. If any debugging action is required, the Verdi system provides another command to “expand” the implicit port – just as if the connection has been specified in detail in the source code, so that users can execute any tracing commands on the connection.

In nTrace, turn on the Source > Expand Implicit Port command to expand the SystemVerilog implicit port statements, the detailed connection will be annotated under the source code, all tracing commands and active annotation are available in the expanded statement. Referring to the following figure, a plus or minus icon will also be created in the line number field, to let you collapse or expand this expanded statement.