Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
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Happy Holidays from SpringSoft!
Engineering Superhero Corner:
SpringSoft Superhero Contest Winner Announced
The SpringSoft community voted Vagner Pires, a design engineer at a large semiconductor company, as having the most creative story about how he overcame design and verification challenges to become an engineering superhero and make a difference in his personal life.
Vagner based the short story on his past experiences having to work nights and weekends to perform tedious debugging tasks, sometimes missing out on quality time with his family. Once he adopted the Verdi System, he was able to quickly find the cause of design errors and correct them, dramatically improving his overall verification cycle and keeping his projects on schedule.
2009 'Best of' Issue!
Verification Tips:
Debug Macros in Verdi - From February
Macros can be defined within or outside of the current scope and can be called multiple times within the design. During debug, engineers may want to see the definition of the macros and signal values within the macro; however, in the conventional approach when engineers encounter a macro, they can only search the macro name in the source code to find the definition and jump to the definition to view the content. The pain of this approach is that it is easy for engineers to forget where the result jumped from when searching the macro content.
Visualizing, Analyzing and Debugging SystemVerilog Testbench Environments - From June
Regardless of the underlying library, the most interesting and useful data for the engineer are the transactions between the sequencer and the driver and between the monitor and analyzers. Ideally, this traffic needs to be recorded into a format that is useful for post-simulation analysis and debug. Because a transaction is a much more convenient high-level encapsulation of data for OVM and VMM-based environments, transaction-level debug visualization and analysis is clearly desirable.
Verdi and Siloti - A Unified and Refined Use Model - From July
In addition to the upcoming Verdi 2009.07 and Siloti 2009.07 releases (scheduled to be released on the 20th of July), a brand new release named "Novas 2009.07" is to be released on the 13th of July. In the new Novas 2009.07 release, the VerdiTM Automated Debug System and the SilotiTM Visibility Automation System are being unified from a use-model and packaging point of view.
Power Aware Debug - From October
The power architecture in today's designs is getting more and more complex, and multiple power domains with many power modes require a thorough verification method. Some technologies are provided to define and verify the complex power domains. Among these technologies, the standard power formats, Common Power Format (CPF)/Unified Power Format (UPF), and power-aware simulation are widely used to ensure that low-power designs still produce a high confidence chip.
IC Design Tips:
Data Management - Auto Check-in and Check-out - From July
Data Management (DM), revision or version control, is used to manage the data and information related to a project. Generally, the project is ongoing and worked on by multiple members of a design team. Only one member of the design team may have write access to modify data files at any given time.
Forward And Backward Compatibility
Software is considered backward (or downward) compatible if newer versions or releases can read, view, and operate on data that was created with prior versions or releases. This should not be confused with forward compatible which means that older software can read, view, and operate on data that has been created with newer releases. Most design automation software is backward compatible.
Technical Articles:
Addressing the Power-Aware Debug Challenge - ECNAsiamag.com, Nov, 2009
When it comes to design verification, one fact is undeniable: as the biggest contributor to design cycle time, it remains a key pain point in the development of today's sophisticated SoCs. As if that weren't a difficult enough challenge to contend with, today's engineers must also now confront concerns over power and its impact on the overall design, verification and implementation process. One reason for the concern is the growing number of applications with their ever increasing functionality that demands low-power operation to support a longer battery life. Increasing power density, driven by higher clock speeds and shrinking process geometries, is another reason for concern over power. Just as critical, is the fact that today's SoCs are often composed of multiple blocks running multiple applications with varying power requirements.
Support:
All Worldwide Support Consolidated To One Site
No matter where you are worldwide, you can now find SpringSoft's top rated support in one place. Just go to http://support.springsoft.com
Product Releases:
See the worldwide support site for the following new product revisions:
A new Novas 2009.10 version, which unifies the VerdiTM Automated Debug System and the SilotiTM Visibility Automation System from a use-model and packaging point of view, was released in October as the default product installation package for Springsoft Novas Debug Solutions, including Verdi and Siloti.
These refinements make it easier and more natural for both Siloti and Verdi users. Users will now be able to access Siloti features through the familiar Verdi interface rather than having to go outside the Verdi flow to prepare and set up for Siloti's unique data expansion capabilities. These improvements will have no impact on licensing.
Novas (Verdi/Siloti): Current release - 2009.10
Laker: Current release - 2009.9 (v5)
Certitude: Current release - 2.7
News:
SpringSoft & Magma Validate Full Interoperability of Custom Chip Design Tools with TSMC 65nm iPDK - Dec. 1, 2009
SAN JOSE, Calif., December 1, 2009 - SpringSoft, Inc. (TAIEX: 2473), a global supplier of specialized IC design software, and Magma® Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software, have completed cross-tool validation using TSMC's 65nm interoperable process design kit (iPDK). The companies demonstrated full interoperability between the SpringSoft LakerTM Custom Layout Automation System and Magma TitanTM Mixed-signal Design Platform running in the OpenAccessTM environment. This validation saves time and effort of setting up an interoperable flow and ensures consistent results.
Upcoming Events:
EDS Fair 2010 - Jan 28-29, 2010
See Springsoft at EDS Fair 2010 in Kanagawa, Japan
Go to: http://edsfair.com/e to learn more.
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We'd appreciate hearing your suggestions, comments or questions about the SpringSoft Newsletter. Please feel free to contact Karim Azar at +1 (408) 467.7860 or karim_azar@springsoft.com
Novas, Laker, Verdi, Siloti and nWave are trademarks and Debussy is a registered trademark of SpringSoft, Inc. All other trademarks are property of their respective owners.
Copyright 2009, SpringSoft, Inc. All rights reserved.
