SpringSoft Technology Newsletter - February 2011
Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
Please see the links at the end of this newsletter for subscription information or to provide feedback that will help us improve future editions.
Verification Enhancement Tips:
Visualize Power Intent in Schematic View
The Power Map window can validate whether all signals between power domains are guarded with isolation rules if a possibility exists that the domain a signal is coming from (‘from’ domain) is off while the domain the signal is going to (‘to’ domain) is not. If this is the case, unexpected results could propagate through such signals from the ‘from’ domain to the ‘to’ domain. Similarly, signals are suggested to be guarded with level-shifter rules if the signals’ ‘from’ and ‘to’ domains are both ‘on’/‘standby’ states but the domains’ voltages are different.
Custom IC Design Tips
Digital Implementation in the Laker Custom Environment
Chances are, if you are the one doing the digital blocks in a “big A , little D” (primarily Analog) environment, you are either handcrafting the digital design from a schematic, or – for larger blocks – sending it out to a megabucks digital place and route tool, and then modifying it afterwards. Either way, you know the pitfalls of these approaches first hand – especially at advanced nodes.
Current Product Versions:
Certitude 2011.01
Verdi/Siloti 2011.01
Laker 2010.11
Laker ADP 2010.11
Laker Test Chip Development platform (T1): 3.2T1v5p1a
Need to update your version? Go to www.springsoft.com/support
Support Notice:
For Novas products and Certitude products, we plan to drop support for following platforms beginning in 2012.01:
Redhat 3 (RHEL3)
SuSE 9 (SLES9)
Events:
See Us At DVCon!
UVM Enhancements Technical Session
Technical Seminars offered by SpringSoft Experts
- Bindesh Patel
- Rex Chen
- Jun Zhao
- Tuesday, March 1, 11AM-12:30PM
- Oak Ballroom
UVM Workshop - Poster Session
Organizers:
- Yatin Trivedi - Accellera
- Dennis Brophy - Accellera
- Stan Krolikoski - Accellera
- Monday Feb 28
- Pine/Cedar Ballroom
Visit us during Exhibition Hours too! Booth #805
- Tuesday & Wednesday, March 1 & 2
- 2PM - 6:30PM
- Bayshore Ballroom
DoubleTree Hotel, San Jose, CA - Click here for more info!
EDA Tech Forum
The Tech Design Forum offers critical technical information for IC designers in an efficient, compact and focused one-day format. This is the only conference that covers the entire design-to-foundry flow to specifically address the needs of the IC designer.
Santa Clara Convention Center
March 10. 2011
SpringSoft Community News!
In the past few months we have added some new features to our website, have you seen them yet?
Video Hints & Tips - Watch quick tips on how to use SpringSoft products more effectively
EDA Blog - Read about and comment on SpringSoft Technology
Find SpringSoft on Twitter and on Facebook.
Twitter: www.twitter.com/SpringSoft
Facebook: www.facebook.com/SpringSoft
We'd appreciate hearing your suggestions, comments or questions about the SpringSoft Newsletter. Please feel free to contact Karim Azar at +1 (408) 467.7860 or karim_azar@springsoft.com
Novas, Laker, Verdi, Siloti and nWave are trademarks and Debussy is a registered trademark of SpringSoft, Inc. All other trademarks are property of their respective owners.
