Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
Please see the links at the end of this newsletter for subscription information or to provide feedback that will help us improve future editions.
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Verification Tips:
Verdi and Siloti - A Unified and Refined Use Model
In addition to the upcoming Verdi 2009.07 and Siloti 2009.07 releases (scheduled to be released on the 20th of July), a brand new release named "Novas 2009.07" is to be released on the 13th of July. In the new Novas 2009.07 release, the VerdiTM Automated Debug System and the SilotiTM Visibility Automation System are being unified from a use-model and packaging point of view.
IC Design Tips:Data Management:
Auto Check-out and Check-in
Data Management (DM), revision or version control, is used to manage the data and information related to a project. Generally, the project is ongoing and worked on by multiple members of a design team. Only one member of the design team may have write access to modify data files at any given time. To modify data, a member will need to check-out the data before making modifications. After modifications are complete, the member will then check-in the data making it available to all of the other design team members.
Technical Articles:
The Quest for Closure - DACeZine June 25, 2009
Engineers responsible for verifying complex circuits and systems are on a quest. They are in uncharted territory, never knowing when they're going to reach their goal and, in fact, not really having a clear idea of exactly where the end zone is located. It's a bit like Columbus sailing the ocean blue: he knew that India was out there somewhere, and thought that if he just sailed far enough he'd run into it. He eventually declared victory even though he wasn't really where he wanted to be. This is a lot like a verification team when it runs out of time for more verification, or when the engineers think they've reached an acceptable level of "coverage."
<Click here to continue reading>
Debugging Power-Aware Designs - Electronics Weekly June 24, 2009
Emerging power fromat standards allow one power definition to be used throughout design, verification and implementation. But they also increase complexity in verification and debugging. This article describes issues engineers face in debugging power-aware designs and the requirements for a solution.
<Click here to continue reading>
Visibility Enhancement Technology Confronts the Visibility Issue with Full-Chip Simulation - IC Design & Verification Journal June 2, 2009
When it comes to system-on-chip verification, two trends have become painfully obvious: it is expensive and it takes too long. Consider, for example, that the most expensive parts of today's SoC design flow are the tasks where the engineer must engage in direct manual effort or expend energy making decisions. In the case of verification, far too much time and money are wasted on tasks that don't add value, such as trying to figure out how supposedly-correct intellectual property (IP) is actually working, debugging "dumb" errors or deciding what signals to record in any given simulation run. While improved design tools and methodologies, coupled with higher levels of abstraction, have made some headway in shortening design and verification times, the time required to determine the root cause of problems found in large, long simulations is growing.
<Click here to continue reading>
News:
Introducing New Additions to the Europe Sales and Support Team
We are pleased to announce that we have strengthened our Europe sales and support with additions to our team. All of these team members bring a great deal of experience to the SpringSoft team and will be responsible for building relationships with our Novas Verification Enhancement (Verdi, Siloti, and Certitude) and Laker Custom IC Design customers in Israel and the rest of Europe.
• Yigal Ben-Eliyahu - Country Manager and Director of Sales for Israel
o yigal_ben-eliyahu@springsoft.com
o +972 979679 887
• Uri Golan - Senior Applications Consultant in Israel for the Laker Custom IC Design Solutions
o uri_golan@springsoft.com
o +972 8 934 8798
• Ross Addinall, PhD. - Senior Applications Consultant in Europe for the Laker Custom IC Design Solutions
o ross_addinall@springsoft.com
o +44 1865 522 659
• Mel Gilmore - Director of Sales for Certitude Functional Qualification System
o mel_gilmore@springsoft.com
o +334 76 43 98 46
• Ali Abara - Senior Applications Consultant for Certitude Functional Qualification System
o ali_abara@springsoft.com
o +334 76 43 91 95
• Olivier Bocquillon - Senior Application Consultant for Certitude Functional Qualification System
o olivier_bocquillon@springsoft.com
o +334 76 43 91 96
SpringSoft and TSMC Commence Joint Development of Multi-Node Process Design Kit Portfolio - June 22, 2009
SpringSoft, Inc. (TAIEX: 2473), a global supplier of specialized IC design software, today announced a multi-year technology agreement with TSMC to jointly develop and validate process design kits (PDKs) for leading-edge chip manufacturing technologies. The collaboration between the two companies is driven by customer demand for SpringSoft PDKs and their mutual support of interoperable PDKs as the long-term goal for providing custom chip designers with the ultimate in manufacturing flexibility, technology choice, and design productivity.
Upcoming Events:
DAC - San Francisco, CA
Booth #3367
July 27-30
Check Out Our Custom IC Design Automation Showcase Featuring Our LakerTM Layout System.
The Laker community of partners will show how tools which are leaders in their own right become even more powerful when they interoperate with Laker, each adding value to the other. The showcase will be running throughout the show in the SpringSoft booth #3367.
Attend Our Free Technical Seminars (SpringSoft booth #3367) - Register Today!
-Interoperability Drives Innovation in Custom IC Design Automation
-How Good Is Your Verification Environment?
-Power-Aware Debug Challenges & Technologies
Don't Miss the Accellera Breakfast Panel
• Frontiers in Verification: Coverage, Closure and Beyond - Click for abstract
• Featuring Real World Engineering Superheroes:
-Scott Runner, Qualcomm
-Avi Ziv, IBM
-Kathy Harrington, AMD
When: Tuesday, July 28 at 7AM
Where: Room 309 in Moscone Center
Get a Demo!
Verification Enhancement Solutions - click for full description
The Verdi Automated Debug System now with:
-Power-aware debug and analysis capabilities
-SVTB debug and analysis capabilities
Siloti Visibility Automation System
-Simulation runtime reduction and file size optimization
Certitude Functional Qualification System - NEW!!
-Objectively measure the quality of your verification environment
-Identify holes in your verification environment
Custom IC Design Automation Solutions - click for full descriptions
The Laker Custom Layout Automation System
Be An Engineering Superhero to the Global Community
Donate Your Used and Unwanted Laptops in Our Booth
We're partnering with Engineers Without Borders and Denali to hold a collection drive for used and unwanted laptops. These laptops will be refurbished and distributed to underprivileged communities around the world.
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We'd appreciate hearing your suggestions, comments or questions about the SpringSoft Newsletter. Please feel free to contact Karim Azar at +1 (408) 467.7860 or karim_azar@springsoft.com
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