SpringSoft Technology Newsletter
July / August 2011
Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
Please see the links at the end of this newsletter for subscription information or to provide feedback that will help us improve future editions.
Functional Closure Tips - Custom IC Design Tips - News - Whitepapers - Technical Articles - Support - Fun Stuff! - Community
Functional Closure Tips:
Mix Full and Essential Dumping Flow with Siloti
The Siloti module of the Novas system provides a flow to dump only essential signals, which efficiently reduces the FSDB file size and speeds up the simulation run. The recommended flow is to use the Essential Signal Dump to analyze the essential signals from the top of the design. This recommendation flow can ensure full visibility when using the Verdi™ Automated Debug System to debug the whole design.
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Custom IC Design Tips
MCell Tcl Callbacks
If you are a user of the Laker Custom Layout system, you are familiar with our Magic Cell (MCell) technology. For the rest of you, MCells are a more advanced, flexible and dynamic way of generating optimized parameterized device layout. The five supported MCell device types are resistors, capacitors, transistors, contact/vias, and guard rings (although only transistors support these Tcl callbacks).
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News:
Sunplus Core Technology Speeds ProtoType Verification of Multimedia ICs with SpringSoft's ProtoLink Probe Visualizer
August 9, 2011
HSINCHU, Taiwan, August 9, 2011 — SpringSoft, Inc., a global supplier of specialized IC design software, today announced that Sunplus Core Technology Co., Ltd. (“SCT”) has accelerated prototype verification of surveillance ICs using the ProtoLink™ Probe Visualizer. Engineers at the Taiwan-based IC design firm specializing in programmable platform solutions have realized dramatic gains in debug productivity for 65-nanometer (nm) design prototypes.
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SpringSoft Moves Toward Speeding Functional Closure
Electronic Design; July 27, 2011
A trio of announcements by SpringSoft unveils a strategy that’s aimed at getting more quickly to what the company terms “functional closure,” or a combination of hardware and software functional signoff. One announcement concerns comprehensive support for the Universal Verification Methodology (UVM) in the Verdi debug suite. The second involves enhancements to the Certitude functional qualification system. The third is a new product, the ProtoLink Probe Visualizer, which simplifies debug of FPGA-based prototyping boards.
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Whitepapers:
Speeding Verification of FPGA-Based Prototype Boards with the ProtoLink Probe Visualizer
It is well-accepted that code review is desirable to ensure the quality of RTL designs. However, from a management perspective, the lack of specific targets beyond coding guidelines often makes it difficult to gain uniform participation, and measure results. Furthermore, traditional code review is incomplete in that it only considers the static RTL, rather than examining it in the full context of how the code is exercised in the test environment.
Free! Download Whitepaper Here
Technical Articles:
Adopting a Flexible FPGA Verification Methodology
SoCCentral.com; June 21, 2011
As system-on-chip (SOC) designs continue to increase in size and complexity, the verification task becomes the bottleneck that can take up to 70% of the overall SOC development effort. As a result, any method that can help to reduce verification cost and achieve verification sign-off earlier is of great interest.
A case study at this year's Design Automation Conference by Taiwan Industrial Technology Research Institute (ITRI) describes an innovative approach to dramatically increase the verification efficiency of a custom-designed FPGA-based prototype board by automating existing in-circuit emulation capabilities and enabling a high-level of visibility into the FPGA(s). This FPGA-based SOC verification platform is a promising new area of interest for ITRI, which is responsible for supporting Taiwanese industry research and development of new technologies and methodologies related to IC design. (See DAC 2011 User Track 2U.7, "A Case Study on Adopting a Flexible FPGA Verification Methodology.")
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Support:
For Novas products and Certitude products, we plan to drop support for following platforms beginning in 2012.01:
Redhat 3 (RHEL3)
SuSE 9 (SLES9)
Check on latest product revisions, get first class product support: Go to www.springsoft.com/support
Latest Product Versions:
Functional Closure:
ProtoLink Probe Visualizer 2011.05
Certitude: 2011.07
Verdi/Siloti 2011.07
Custom IC Design:
Laker Proprietary DB (aka Laker-DB): Laker-2011.02p4 (released on 2011/7/6)
Laker Open Access DB: laker-OA2011.03p1 (released on 2011/06/17)
Laker ADP Proprietary DB: Laker_ADP-2011.02p4 (released on 2011/07/06)
Laker ADP Open Access DB: Laker_ADP-OA201103p2 (released on 2011/07/21)
Laker T1 Proprietary DB: Laker_TCD-201105 (released on 2011/6/11)
Fun Stuff!
Did you miss our super-cool video games at DAC?!?!?!
You got another chance to play! Check them out:
SpringSoft Community News!
Video Hints & Tips - Watch quick tips on how to use SpringSoft products more effectively
EDA Blog - Read about and comment on SpringSoft Technology
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We'd appreciate hearing your suggestions, comments or questions about the SpringSoft Newsletter. Please feel free to contact Karim Azar at +1 (408) 467.7860 or karim_azar@springsoft.com
Laker, Verdi, Siloti and ProtoLink are trademarks of SpringSoft, Inc. All other trademarks are property of their respective owners.
