Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
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Verification Tips:
Visualizing, Analyzing and Debugging SystemVerilog Testbench Environments
Regardless of the underlying library, the most interesting and useful data for the engineer are the transactions between the sequencer and the driver and between the monitor and analyzers. Ideally, this traffic needs to be recorded into a format that is useful for post-simulation analysis and debug. Because a transaction is a much more convenient high-level encapsulation of data for OVM and VMM-based environments, transaction-level debug visualization and analysis is clearly desirable.
IC Design Tips:
Basics of Data Management
Data Management (DM) allows a design team to manage and track the creation, editing, and archiving of all data and information related to a project. The data is kept in a central repository and the data management tool will control the check-in and check-out of files to a multi-user community of designers, insuring that only one user has write access to the data at a given time.
Technical Articles:
Visualizing, analyzing and debugging SystemVerilog testbench environments - EDA DesignLine; May 1, 2009
SystemVerilog, and the verification methodologies that have sprung up around it, have enabled a significant leap forward in testbench automation and allow for generation of sophisticated stimulus scenarios.
This level of sophistication and automation requires a corresponding leap in debug capabilities within such environments. Advanced logging and interactive inspection provide an ideal means of recording transactions from the testbench and subsequently, allowing visualization and analysis of these transactions.
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Employ advanced logging techniques for SystemVerilog - EE Times Asia, May 1, 2009
SystemVerilog provides an advantage in addressing the verification complexity challenge-not simply as a new language for describing complex structures, but as a platform for driving a more efficient, realistic test of the design. It is no surprise then that the adoption of the language for verification purposes has been rapid. However, there is a gap when it comes to the debug and analysis of SystemVerilog testbench code. The accepted "dumpvars"-based techniques are not practical for the software-like object-oriented testbench code, and their benefits in this realm are also questionable. But, at the end of the day, engineers do need to know what the testbench is doing at any given point in time. Thus far, engineers have been forced to revert to low-level, text-based message logging and subsequent manual analysis of the resulting text log files.
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Environment de Verification - Electronique May 2009
Visibility Enhancement Technology Confronts the Visibility Issue with Full-Chip Simulation - IC Design & Verification Journal, June 2, 2009
When it comes to system-on-chip verification, two trends have become painfully obvious: it is expensive and it takes too long. Consider, for example, that the most expensive parts of today's SoC design flow are the tasks where the engineer must engage in direct manual effort or expend energy making decisions. In the case of verification, far too much time and money are wasted on tasks that don't add value, such as trying to figure out how supposedly-correct intellectual property (IP) is actually working, debugging "dumb" errors or deciding what signals to record in any given simulation run. While improved design tools and methodologies, coupled with higher levels of abstraction, have made some headway in shortening design and verification times, the time required to determine the root cause of problems found in large, long simulations is growing.
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News:
SPRINGSOFT, INTRODUCES STRUCTURED METHOD FOR SYSTEMVERILOG TESTBENCH DEBUG AND ANALYSIS
Hsinchu, Taiwan, May 18, 2009 - SpringSoft, Inc. (TAIEX: 2473), a global supplier of specialized IC design software, today announced comprehensive SystemVerilog Testbench (SVTB) debug support with the latest release of its award-winning VerdiTM Automated Debug System. The Verdi system introduces a new structured message-based method for automating SVTB debug so engineers can quickly comprehend complex testbench behavior. The Verdi SVTB debug solution is fully integrated with SpringSoft's family of NovasTM Verification Enhancement products that let engineers do more verification in less time.
Upcoming Events:
DAC - San Francisco, CA
Booth #3367
July 27-30
TSMC China Symposium Expo
Date: June 25
Location: Shanghai International Convention Center (SICC), Shanghai, China
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