SpringSoft Technology Newsletter
June 2011
Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
Please see the links at the end of this newsletter for subscription information or to provide feedback that will help us improve future editions.
Functional Closure Tips - Custom IC Design Tips - News - Whitepapers - Technical Articles - Support - Fun Stuff! - Community
Functional Closure Tips:
Correlate Gate to RTL with User Defined Map File
When debugging errors at the gate-level verification stage, designers usually need to refer to the golden RTL design to determine what went wrong. For example, if an error value is found in a signal, designers may compare the waveform of the signal and its related driving signals with the correlating signals in the RTL design to debug for any mismatches. In regular practice, the correlation between gate-level and RTL designs is manually conducted by designers. This process is often complicated and consumes precious time.
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Custom IC Design Tips
Turning the Corner in Laker ADP
The latest releases of the Laker Advanced Design Platform (ADP) consist of a completely reworked schematic editor, an enhanced Simulation Console, and an integrated waveform analyzer. In the 2011.02 version of Laker ADP, corner sweeps for Temperature,Variables and Model Files are supported so that you can manage all PVT (process,voltage and temperature) sweeps in a GUI and simulate over all states with veryfew clicks. When submitted, the simulation processes for all corner sweeps are sequentially submitted to multiple machines that you designate. This makes simulation over different PVT states much more efficient.
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News:
SpringSoft's Laker Custom Layout System Selected for TSMC 28NM Reference Flows
HSINCHU, Taiwan, June 6, 2011 — SpringSoft, Inc., a global supplier of specialized IC design software, today announced that its Laker™ Custom Layout Automation System is selected by Taiwan Semiconductor Manufacturing Company (TSMC) for the company’s 28-nanometer (nm) Analog and Mixed-Signal (AMS) Reference Flow 2.0 and Reference Flow 12.0 for digital design.
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SpringSoft's New ProtoLink Probe Visulaizer Speeds Verification of FPGA-Based Prototype Boards
HSINCHU, Taiwan, May 23, 2011 — SpringSoft, Inc., a global supplier of specialized IC design software, today introduced the ProtoLink™ Probe Visualizer to dramatically increase design visibility and simplify debug of FPGA-based prototype boards. The new Probe Visualizer uses patented interconnect innovations and software automation with the industry-leading HDL debug platform to shorten the verification cycle of off-the-shelf or custom-designed prototypes and maximize their return on investment for early validation of system-on-chip (SoC) designs.
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SpringSoft's Verdi debug Software Expands Verification Interoperability with Comprehensive UVM Support
HSINCHU, Taiwan, May 2, 2011 — SpringSoft, Inc., a global supplier of specialized IC design software, today announced comprehensive support for the Universal Verification Methodology (UVM) with its Verdi™ Automated Debug System. The Verdi software adds UVM source code and new transaction recording capabilities to its existing HDL debug platform, making it easier for engineers to visualize and debug the complex SystemVerilog testbench structures required to test sophisticated system-on-chip (SoC) devices.
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Whitepapers:
Speeding Verification of FPGA-Based Prototype Boards with the ProtoLink Probe Visualizer
It is well-accepted that code review is desirable to ensure the quality of RTL designs. However, from a management perspective, the lack of specific targets beyond coding guidelines often makes it difficult to gain uniform participation, and measure results. Furthermore, traditional code review is incomplete in that it only considers the static RTL, rather than examining it in the full context of how the code is exercised in the test environment.
Free! Download Whitepaper Here
Technical Articles:
Adopting a Flexible FPGA Verification Methodology
SoCCentral.com; June 1, 2011
As system-on-chip (SOC) designs continue to increase in size and complexity, the verification task becomes the bottleneck that can take up to 70% of the overall SOC development effort. As a result, any method that can help to reduce verification cost and achieve verification sign-off earlier is of great interest.
A case study at this year's Design Automation Conference by Taiwan Industrial Technology Research Institute (ITRI) describes an innovative approach to dramatically increase the verification efficiency of a custom-designed FPGA-based prototype board by automating existing in-circuit emulation capabilities and enabling a high-level of visibility into the FPGA(s). This FPGA-based SOC verification platform is a promising new area of interest for ITRI, which is responsible for supporting Taiwanese industry research and development of new technologies and methodologies related to IC design. (See DAC 2011 User Track 2U.7, "A Case Study on Adopting a Flexible FPGA Verification Methodology.")
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Support:
For Novas products and Certitude products, we plan to drop support for following platforms beginning in 2012.01:
Redhat 3 (RHEL3)
SuSE 9 (SLES9)
Check on latest product revisions, get first class product support: Go to www.springsoft.com/support
Fun Stuff!
Did you miss our super-cool video games at DAC?!?!?!
You got another chance to play! Check them out:
SpringSoft Community News!
Video Hints & Tips - Watch quick tips on how to use SpringSoft products more effectively
EDA Blog - Read about and comment on SpringSoft Technology
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We'd appreciate hearing your suggestions, comments or questions about the SpringSoft Newsletter. Please feel free to contact Karim Azar at +1 (408) 467.7860 or karim_azar@springsoft.com
Laker, Verdi, Siloti and ProtoLink are trademarks of SpringSoft, Inc. All other trademarks are property of their respective owners.
