SpringSoft Technology Newsletter - March 2011
Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
Please see the links at the end of this newsletter for subscription information or to provide feedback that will help us improve future editions.
Verification Enhancement Tips - Custom IC Design Tips - News - Whitepapers - Support - Events - Community
Verification Enhancement Tips:
Fault Dropping Improves Certitude™ Efficiency & Quality of Results
One important goal of the Certitude development team is to continually improve the quality of the results presented to the user for analysis. By quality, we mean relevance to “big problems” in the user’s verification environment and uniqueness – the likelihood that any given non-detected (ND) fault from a particular iteration of the tool points to a problem that is different than the other ND faults. A related goal is efficiency – the quick isolation of a few important problems that should be investigated and fixed before continuing. One of the processes that greatly improves both quality of results and efficiency is fault dropping.
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Use Batch Mode Behavior Analysis (BACOM) to Reduce Time to Bring Up Siloti Session
The Siloti™ Visibility Automation System (part of the Novas Verification Enhancement Solutions) needs to perform Behavior Analysis on the related design scopes when the Data Expansion command is used for the first time. When this happens, users need to wait for the Behavior Analysis process to finish. The waiting period makes the usage of the Data Expansion command difficult.
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Custom IC Design Tips
ADP Hierarchy Editor
The Hierarchy Editor window has been introduced in the Laker™ Advanced Design Platform (ADP) to allow easy switching among view types for netlists. Users can create the configuration to specify the binding view for each cell/instance and then review the binding for the whole design on the cell level, instance level or each level through the entire hierarchy via the Table View or the hierarchy Tree View. The binding configuration is saved as a config view in ADP.
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News:
SpringSoft Completes OpenAccess-compatible IC Layout Flow with Enhancements to Laker ADP Design Entry System
HSINCHU, Taiwan, March 14, 2011 — SpringSoft, Inc., a global supplier of specialized IC design software, today announced the availability of the latest version of its Laker™ Advanced Design Platform (ADP) design entry tool, completing its front-to-back custom IC layout flow based on the OpenAccess (OA) standard. The new software release also includes a host of productivity-enhancing features and improvements for design entry, analysis and navigation.
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SpringSoft's Laker Leads the Way to SignOff-Driven Custom Layout Flow with Integration of Calibre RealTime
HSINCHU, Taiwan, March 11, 2011 — SpringSoft, Inc., a global supplier of specialized IC design software, today introduced a new signoff-driven layout flow with its Laker™ Custom Layout software and the new Calibre® RealTime platform, announced separately today by the Mentor Graphics® Corporation. The Calibre RealTime platform provides instantaneous design rule checking (DRC) in the Laker OpenAccess (OA) layout environment for sign-off quality physical verification during design creation. This unique capability enables Laker users to generate high quality custom layouts in less time and get to foundry sign-off sooner, even at the most advanced technology nodes. The Laker signoff-driven layout flow is immediately available with the latest Laker OA software release.
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SpringSoft, Dongbu Hitek Release First in Series of Laker Process design Kits to Streamline Custom Chip Design
HSINCHU, Taiwan, March 8, 2011 — SpringSoft, Inc.,a global supplier of specialized IC design software, and Dongbu HiTek Co., Ltd., a world leader of specialized foundry technologies and services based in South Korea, today announced a multi-year partner program to jointly develop a series of process design kits (PDKs) that streamline implementation of custom chips with Dongbu’s leading-edge manufacturing technologies at mature process nodes. The companies also announced the release today of the SpringSoft Laker™ PDK for the Dongbu HiTek 0.18-micron BCDMOS foundry process with additional PDKs to follow throughout 2011.
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Making Great Products Great - EDN.com
Verilab VP JL Gray moderated one of the best executive panels at DVCon ever. Speakers from a range of industries declared that getting great products to market is never about luck, but always about managing the Team, the Vision, and the Expectations that drive them.
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Essential Signal Data and Siloti - SemiWiki.com
One of the challenges with verifying today's large chips is deciding which signals to record during simulation so that you can work out the root cause when you detect something anomalous in the results. If you record too few signals, then you risk having to re-run the entire simulation when you omitted to record a signal that turns out to be important. If you record too many, or simply record all the signals to be on the safe side, then the simulation time can get prohibitively long. In either case, re-running the simulation or running it very slowly, the time taken for verification increases unacceptably.
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SpringSoft's Siloti & Verdi Play Together - GabeanEDA.com
SpringSoft, Inc. has integrated an enhanced version of its Siloti™ Visibility Automation System with the Verdi™ Automated Debug System. Siloti now offers a streamlined, easy-to-use flow for system-on-chip (SoC) verification and debug. The latest software release incorporates a new reusable behavior analysis database to eliminate redundant analysis cycles and speed up design preparation time by at least 10X over previous releases during debug operations.
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Reusable Behavior Analysis Database Eliminates Redundant SoC Design Analysis Cycles - EETimes Europe
SpringSoft launched the Siloti visibility automation system, offering a streamlined flow for SoC verification and debug. The latest software release incorporates a new reusable behavior analysis database to eliminate redundant analysis cycles, which speeds up design preparation time by at least 10X over previous releases during debug operations with the company’s Verdi automated debug system.
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Siloti System Simplifies SoC Verification & Debug - Components in Electronics
SpringSoft, a supplier of specialised IC design software, has launched the Siloti Visibility Automation System which offers a new streamlined, easy-to-use flow for system-on-chip (SoC) verification and debug. The latest software release incorporates a new reusable behaviour analysis database to eliminate redundant analysis cycles and speed up design preparation time by at least 10X over previous releases during debug operations with SpringSoft’s Verdi Automated Debug System.
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Whitepapers:
Schematic-Driven Layout Automation
Circuit designs continue to get larger and more complicated. As a rule of thumb, layout productivity must double with every new process node in order to keep pace with Moore’s law. For digital implementation, the automatic place and route (AP&R) tools have done a good job of keeping pace. However, productivity gains are harder to achieve for custom IC design. By its nature, custom (transistor-level) design still tends to be done largely by hand by circuit experts. Even when the analog content of today’s SOCs is relatively small, it is not uncommon for the analog portion of the chip to become the gating item in the tapeout schedule.
Free! Download Whitepaper Here
Current Product Versions:
Certitude 2011.01
Verdi/Siloti 2011.01
Laker 2010.11
Laker ADP 2010.11
Laker Test Chip Development platform (T1): 3.2T1v5p1a
Need to update your version? Go to www.springsoft.com/support
Support Notice:
For Novas products and Certitude products, we plan to drop support for following platforms beginning in 2012.01:
Redhat 3 (RHEL3)
SuSE 9 (SLES9)
Events:
See Us At SUNG!
Designer Community Expo
Monday, March 28, 2011, 4:30-7:30pm
Santa Clara Convention Center
Click here for more info
TSMC U.S. Technology Symposium
Tuesday, April 5, 2011
McEnery Convention Center, San Jose, CA
SpringSoft Community News!
Video Hints & Tips - Watch quick tips on how to use SpringSoft products more effectively
EDA Blog - Read about and comment on SpringSoft Technology
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We'd appreciate hearing your suggestions, comments or questions about the SpringSoft Newsletter. Please feel free to contact Karim Azar at +1 (408) 467.7860 or karim_azar@springsoft.com
Novas, Laker, Verdi, Siloti and nWave are trademarks and Debussy is a registered trademark of SpringSoft, Inc. All other trademarks are property of their respective owners.
