SpringSoft Technology Newsletter
May 2011
Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
Please see the links at the end of this newsletter for subscription information or to provide feedback that will help us improve future editions.
Functional Closure Tips - Custom IC Design Tips - News - Whitepapers - Support - Events - Community
Functional Closure Tips:
How to automatically record UVM transactions into the FSDB
SVTB-based testbench environments are typically built on top of an SVTB verification library/methodology like UVM. SpringSoft has leveraged the infrastructure provided in UVM to record transactions flowing up and down the testbench into the FSDB file. The mechanism replaces the UVM’s transaction recording capability with the SpringSoft modified version. When the SpringSoft transactions recording files are integrated (replacing the original UVM ones) to the user’s UVM library and a transaction event occurs, the transaction data will be automatically recorded to the FSDB file.
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Custom IC Design Tips
Turning the Corner in Laker ADP
The latest releases of the Laker Advanced Design Platform (ADP) consist of a completely reworked schematic editor, an enhanced Simulation Console, and an integrated waveform analyzer. In the 2011.02 version of Laker ADP, corner sweeps for Temperature,Variables and Model Files are supported so that you can manage all PVT (process,voltage and temperature) sweeps in a GUI and simulate over all states with veryfew clicks. When submitted, the simulation processes for all corner sweeps are sequentially submitted to multiple machines that you designate. This makes simulation over different PVT states much more efficient.
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News:
SpringSoft's Verdi debug Software Expands Verification Interoperability with Comprehensive UVM Support
HSINCHU, Taiwan, May 2, 2011 — SpringSoft, Inc., a global supplier of specialized IC design software, today announced comprehensive support for the Universal Verification Methodology (UVM) with its Verdi™ Automated Debug System. The Verdi software adds UVM source code and new transaction recording capabilities to its existing HDL debug platform, making it easier for engineers to visualize and debug the complex SystemVerilog testbench structures required to test sophisticated system-on-chip (SoC) devices.
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SpringSoft Rolls Out Advanced Technology Platform for Certitude Functional Qualification System
HSINCHU, Taiwan, May 11, 2011 — SpringSoft, Inc., a global supplier of specialized IC design software, today announced advancements to its Certitude™ Functional Qualification System that enable broader and more efficient deployment of verification qualification methodologies. New detection automation and checker qualification capabilities are among the key innovations developed to quickly identify potential problems in chip verification environments with fewer resources and drive continuous improvements throughout the verification flow.
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SpringSoft's Verdi Improves Efficiency of VLSI Research and Development and Design Education at Japan's VDEC
YOKOHAMA, Japan, May 18, 2011 — SpringSoft, Inc., a global supplier of specialized IC design software, today announced that VLSI Design and Education Center (VDEC) will provide SpringSoft’s Verdi™ Automated Debug System to national universities, public universities, private universities and colleges in Japan for educational programs. VDEC is an intellectual education center on VLSI (Very Large Scale Integration) technology chartered to improve VLSI design education and support for VLSI chip fabrication in Japan’s semiconductor industry.
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SpringSoft's New ProtoLink Probe Visulaizer Speeds Verification of FPGA-Based Prototype Boards
HSINCHU, Taiwan, May 23, 2011 — SpringSoft, Inc., a global supplier of specialized IC design software, today introduced the ProtoLink™ Probe Visualizer to dramatically increase design visibility and simplify debug of FPGA-based prototype boards. The new Probe Visualizer uses patented interconnect innovations and software automation with the industry-leading HDL debug platform to shorten the verification cycle of off-the-shelf or custom-designed prototypes and maximize their return on investment for early validation of system-on-chip (SoC) designs.
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Whitepapers:
Speeding Verification of FPGA-Based Prototype Boards with the ProtoLink Probe Visualizer
It is well-accepted that code review is desirable to ensure the quality of RTL designs. However, from a management perspective, the lack of specific targets beyond coding guidelines often makes it difficult to gain uniform participation, and measure results. Furthermore, traditional code review is incomplete in that it only considers the static RTL, rather than examining it in the full context of how the code is exercised in the test environment.
Free! Download Whitepaper Here
Support:
For Novas products and Certitude products, we plan to drop support for following platforms beginning in 2012.01:
Redhat 3 (RHEL3)
SuSE 9 (SLES9)
Check on latest product revisions, get first class product support: Go to www.springsoft.com/support
Events:
Design Automation Conference
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June 6-8, 2011 |
SpringSoft Community News!
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We'd appreciate hearing your suggestions, comments or questions about the SpringSoft Newsletter. Please feel free to contact Karim Azar at +1 (408) 467.7860 or karim_azar@springsoft.com
Laker, Verdi, Siloti and ProtoLink are trademarks of SpringSoft, Inc. All other trademarks are property of their respective owners.
