SpringSoft Technology Newsletter November 2010
Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
Please see the links at the end of this newsletter for subscription information or to provide feedback that will help us improve future editions.
Verification Enhancement Tips:
Power-aware Debug for Gate Level Designs
When the RTL design is converted to a gate-level design, part of the power intent defined in CPF
(CommonPower Format )/UPF(UPF - the IEEE 1801-2009 standard) power files is 'synthesized' either by a synthesis tool or by the designers manually. For example, the isolation, level-shifter and retention rules are implemented by inserting isolation, level-shifters and retention cells during the conversion from RTL to gate level design. Along with the conversion, the content of the CPF/UPF files should be refined by the tool or designers respectively to reflect the changes.
Certitude™ Non-Detected Faults: Results Analysis Considerations
If you are a Certitude user, you know that non-detected (ND) faults are the typical starting points for the results analysis process. An ND fault indicates that Certitude has propagated the effect (incorrect operation) of an injected fault to the boundary (outputs) of the design, but the verification environment (VE) does not detect it. This typically indicates some deficiency in the VE's checking infrastructure – perhaps an incomplete or altogether missing checker that can let RTL bugs escape the verification process undetected. This article considers two important issues to consider when investigating an ND fault: The "size" of the design change implied by the fault and the origin of the problem that led to the VE weakness.
Custom IC Design Tips
Using Laker-T1 Test Chip Development Platform for DRC Validation
Many Laker customers are familiar with the Laker-T1 TCD (Test Chip Development) platform. After all, it has been used by many of the world's top foundries and fabs for automated test line and test chip development. The simple GUI interfaces in Laker-T1 allow process development engineers with little or no layout experience to develop comprehensive parameterized test suites.
Technical Articles:
A Next-gen FPGA-based SoC Verifcation Platform - EE Times, November 2010
System-on-Chip (SoC) designs continue to increase in size and complexity. At the same time, market windows are shrinking and today's electronic markets are extremely sensitive to time-to-market pressures. All of this is putting tremendous demands on SoC design and verification teams. Indeed, it is now widely accepted that verification accounts for around 70 percent of the total SoC development cycle.
Current Product Versions:
Certitude 2010.07
Verdi/Siloti 2010.07
Laker 2010.05 (Open Access version)
ADP 2010.02 (Open Access version)
Laker 2010.03 (Laker db version)
ADP 2010.03 (Laker db version)
Need to update your version? Go to www.springsoft.com/support
Support Notice:
For Novas products and Certitude products, we plan to drop support for following platforms beginning in 2012.01:
Redhat 3 (RHEL3)
SuSE 9 (SLES9)
SpringSoft Community News!
In the past few months we have added some new features to our website, have you seen them yet?
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We'd appreciate hearing your suggestions, comments or questions about the SpringSoft Newsletter. Please feel free to contact Karim Azar at +1 (408) 467.7860 or karim_azar@springsoft.com
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