Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
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Verification Tips:
Power Aware Debug
The power architecture in today's designs is getting more and more complex, and multiple power domains with many power modes require a thorough verification method. Some technologies are provided to define and verify the complex power domains. Among these technologies, the standard power formats, Common Power Format (CPF)/Unified Power Format (UPF), and power-aware simulation are widely used to ensure that low-power designs still produce a high confidence chip.
IC Design Tips:
Advanced Schematic-Driven Layout
Advanced schematic-driven layout provides controlled automation that offers benefits over manual layout and earlier schematic-driven flows. With the advances SDL automation of the Laker system, designers can focus more on results and less on parameters, connectivity, and design rules. The unique advanced technologies and features of the Laker Custom Layout System go far beyond simple drag and drop device generation to make layout creation easier and faster, helping designers create superior layout with less effort.
Technical Papers:
Introducing Functional Qualification
Functional verification consumes a significant portion of the time and resources devoted to the typical design project. As chips continue to grow in size and complexity, designers must increasingly rely on a dedicated verification team to ensure that systems fully meet their specifications. Verification engineers have at their disposal a set of dedicated tools and methodologies for verification automation and quality improvement. In spite of this, functional logic errors remain a significant cause of project delays and re-spins.
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Technical Articles:
Layout Automation for the Next Generation of Chips - ECNAsia.com, October 2009
Like most steps in the IC design flow, custom layout is becoming more tedious, complex and time consuming. To keep up with increasing die size, tight time-to-market requirements and new process-induced layout constraints, automation of the design process must constantly increase. Schematic-driven layout (SDL) is an automated capability that assists designers with the custom physical implementation of circuits (both analog and digital). SDL provides significantly faster layout by automatically maintaining continuity between logic and layout. SDL relies on device generation technology to automate the creation of physical layout from schematic elements.
The Next Leap Forward - Components in Electronics, September 2009
According to Moore's Law, the number of transistors that can be placed on an integrated circuit (IC) increases exponentially, doubling approximately every two years. While the semiconductor industry has taken full advantage of this scaling, steadily increasing the number of components per chip, more components translate into greater design complexity and an increase in the amount of time required to complete a design.
Support:
All Worldwide Support Consolidated To One Site
No matter where you are worldwide, you can now find SpringSoft's top rated support in one place. Just go to http://support.springsoft.com
Product Releases:
A new Novas 2009.10 version, which unifies the VerdiTM Automated Debug System and the SilotiTM Visibility Automation System from a use-model and packaging point of view, is released as the default product installation package for Springsoft Novas Debug Solutions, including Verdi and Siloti.
These refinements make it easier and more natural for both Siloti and Verdi users. Users will now be able to access Siloti features through the familiar Verdi interface rather than having to go outside the Verdi flow to prepare and set up for Siloti's unique data expansion capabilities. These improvements will have no impact on licensing.
See the worldwide support site for the following new product revisions:
Verdi: Current release - 2009.10
Siloti: Current release - 2009.10
Laker: Current release - 3.2v4P3a ; Upcoming release - 2009.9v5
Certitude: Current release - 2.7
News:
HOYA Adopts SpringSoft Laker System For Custom Chip Design
Hsinchu, Taiwan, September 14, 2009 - SpringSoft, Inc., a global supplier of specialized IC design software, today announced that the Mask Division of Japan tech giant HOYA Corporation adopted the LakerTM Custom Layout System in Japan and China. The Laker software enables HOYA design teams to support the diverse requirements of chip companies across the globe with a consistent, proven implementation flow from design specification through semiconductor mask generation.
Upcoming Events:
SpringSoft Community Conferences
Engineering Superhero
Corner:
Be An Engineering Superhero to the Global Community
SpringSoft is working with the Engineers Without Borders Labdoo Project to bring the excess supply of technology from our developed world to developing regions throughout the globe. At this year's DAC, we kicked off the program with a collection drive for used and unwanted laptops that will be refurbished and distributed to disadvantaged communities. We will continue to collect laptops on behalf of Engineers Without Borders Labdoo Project.
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We'd appreciate hearing your suggestions, comments or questions about the SpringSoft Newsletter. Please feel free to contact Karim Azar at +1 (408) 467.7860 or karim_azar@springsoft.com
Novas, Laker, Verdi, Siloti and nWave are trademarks and Debussy is a registered trademark of SpringSoft, Inc. All other trademarks are property of their respective owners.
Copyright 2009, SpringSoft, Inc. All rights reserved.
