SpringSoft Technology Newsletter
September 2011
Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.
Please see the links at the end of this newsletter for subscription information or to provide feedback that will help us improve future editions.
Functional Closure Tips - Custom IC Design Tips - News - Whitepapers - Technical Articles - Support - Fun Stuff! - Community
Functional Closure Tips:
Automatically Record UVM 1.1 Sequencer Transactions
In addition to the previously supported UVM 1.0 and UVM 1.0p1 versions, now you will be able to automatically record UVM 1.1 sequencer transactions into the FSDB file.
The automatic
sequencer transaction recording for UVM 1.1 will be provided in the upcoming Novas
2011.10 release. Currently, the support for UVM 1.1 is considered beta.
The supported simulators are Synopsys VCS, Cadence IUS and Mentor’s ModelSim.
Click Here
Custom IC Design Tips
Removing Orphan MCells
MCells™, the highly flexible, built-in parameterized devices in theLaker™ Custom Layout System, are automatically cached whenever a unique MCell isplaced or created in the layout. Caching dramatically speeds up display times comparedto constantly recreating the layout each time an MCell is opened for viewing.One potential drawback of caching is that you can end up with "orphan" MCells(unused versions) in your library. If you have excessive numbers of MCellorphans, it can contribute to slower display speeds.
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News:
Technical Contributions Advance Si2's OpenPDK Coalition Progress
The Silicon Integration Initiative (Si2) announced today that since the
Open Process Design Kit (OpenPDK) Coalition’s founding approximately one
year ago, it has received essential technical contributions, as well as
significant collaborations by the 16 member companies in its Working
Groups, toward defining a truly open PDK structure for the industry.
Process Design Kits (PDKs) are at the core of enabling custom/analog
design, verification, and implementation, and are increasingly complex
at advanced nodes, including 28 and 20 nanometer processes which are
currently being qualified.
Continue Reading
Whitepapers:
Speeding Verification of FPGA-Based Prototype Boards with the ProtoLink Probe Visualizer
It is well-accepted that code review is desirable to ensure the quality of RTL designs. However, from a management perspective, the lack of specific targets beyond coding guidelines often makes it difficult to gain uniform participation, and measure results. Furthermore, traditional code review is incomplete in that it only considers the static RTL, rather than examining it in the full context of how the code is exercised in the test environment.
Free! Download Whitepaper Here
Technical Articles:
Adopting a Flexible FPGA Verification Methodology
SoCCentral.com; June 21, 2011
As system-on-chip (SOC) designs continue to increase in size and complexity, the verification task becomes the bottleneck that can take up to 70% of the overall SOC development effort. As a result, any method that can help to reduce verification cost and achieve verification sign-off earlier is of great interest.
A case study at this year's Design Automation Conference by Taiwan Industrial Technology Research Institute (ITRI) describes an innovative approach to dramatically increase the verification efficiency of a custom-designed FPGA-based prototype board by automating existing in-circuit emulation capabilities and enabling a high-level of visibility into the FPGA(s). This FPGA-based SOC verification platform is a promising new area of interest for ITRI, which is responsible for supporting Taiwanese industry research and development of new technologies and methodologies related to IC design. (See DAC 2011 User Track 2U.7, "A Case Study on Adopting a Flexible FPGA Verification Methodology.")
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Support:
For Novas products and Certitude products, we plan to drop support for following platforms beginning in 2012.01:
Redhat 3 (RHEL3)
SuSE 9 (SLES9)
Check on latest product revisions, get first class product support: Go to www.springsoft.com/support
Latest Product Versions:
Functional Closure:
ProtoLink Probe Visualizer 2011.05
Certitude: 2011.07
Verdi/Siloti 2011.07
Custom IC Design:
Laker Proprietary DB (aka Laker-DB): Laker-2011.02p4 (released on 2011/7/6)
Laker Open Access DB: laker-OA2011.03p1 (released on 2011/06/17)
Laker ADP Proprietary DB: Laker_ADP-2011.02p4 (released on 2011/07/06)
Laker ADP Open Access DB: Laker_ADP-OA201103p2 (released on 2011/07/21)
Laker T1 Proprietary DB: Laker_TCD-201105 (released on 2011/6/11)
Fun Stuff!
Did you miss our super-cool video games at DAC?!?!?!
You got another chance to play! Check them out:
SpringSoft Community News!
Video Hints & Tips - Watch quick tips on how to use SpringSoft products more effectively
EDA Blog - Read about and comment on SpringSoft Technology
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We'd appreciate hearing your suggestions, comments or questions about the SpringSoft Newsletter. Please feel free to contact Karim Azar at +1 (408) 467.7860 or karim_azar@springsoft.com
Laker, Verdi, Siloti and ProtoLink are trademarks of SpringSoft, Inc. All other trademarks are property of their respective owners.
