Scaling Custom digital Layout for Next-Generation Chip Design

By Rich Morse
Technical Marketing
EDA Alliances Manager
Laker Custom IC Design Products
SpringSoft Inc.

Mitch Heins
VP of Applications
Pyxis Technology Inc.

Layout for large digital IC designs is generally created using highly automated place-and-route (APR) tools. Although there are trade-offs for using APR instead of custom layout, the speed and confidence offered by APR far out weigh the compromises in area or performance for most designs. But designs that require the utmost in performance and/or the smallest possible area are still done "by hand" using custom IC layout methodologies.

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