In late 2006, five electronic design automation (EDA) software companies came together and agreed to collaborate on the creation and distribution of an interoperable Pcell library (IPL) and an open infrastructure for its use. This proof-of-concept Pcell library was developed and released in less than six months, and was soon operating in eight different tools from five different EDA companies. The success of this unlikely gathering of competitors shows that the benefits of collaboration extend all the way into the IC design tool supply chain.

The “Old” Way

Historically, IC design systems have consisted of collections of software point tools, glued together into a workable design methodology through the use of extensive software scripting and multiple data format translations. This method has long been used - sometimes even by software tool vendors within their own tool sets - to bring together “silos” of application expertise to create more efficient design “flows” consisting of tools that could not otherwise interoperate. Users claim that design tool integration can cost them $2 to $4 (or more) for every dollar spent on commercial EDA software tools. A parallel in semiconductor manufacturing can be found in the days when wafer processes were a chain of discrete process steps - often defined by the hardware tools themselves - between which wafers were transported by hand. Eventually, customers who demanded and implemented machine interface standards, automated wafer handling and factory automation software gained huge efficiencies. The equipment industry supply chain came together to develop standards, and everybody (i.e., suppliers, fabs and customers) benefited from collaboration. Today, there are many EDA standards that have made these glued-together design flows possible, but not nearly enough has been done to provide an infrastructure for seamless interoperability. The IPL Initiative is an active example of a group collaborating to create an open environment for the custom and analog design domain.

When the founding members of this group first met, the first order of business was to agree upon the adoption of an open database standard for EDA databases. In the past, EDA companies developed proprietary databases either by necessity or because they felt their unique version offered a competitive advantage for their own particular products. Access to these proprietary databases by outside vendors was granted only to certain value-added, third-party tools and generally involved hidden data translations to pass information between tools. Because innovation often takes place at small start-ups, companies that merged, or those that acquired technology through acquisition, found themselves with an internal “Tower of Babel” wherein every tool spoke a different database “language.” Naturally, this problem was worse for customers who tried to create best-in-class design flows using tools from different vendors or tried to integrate commercial tools with their own proprietary tools.

The Open Database Challenge

In 2001, after decades of unsuccessful efforts by other groups, Si2 hosted a committee to define and develop an open database standard. In spite of initial competitive concerns, today, this open database standard is available to all interested parties, and it is generally accepted that it will be adopted as an industry standard database, at least for custom and analog design. Today, there are approximately 34 major EDA vendor companies, accounting for over 80% of EDA revenue, and major customers collaborating to develop and maintain this database standard. This number of companies speaks volumes about the value of collaboration for design success. But while adoption of this standard is a good start, it is not enough. The availability of an “open” database - like an open operating system (e.g., Linux) - does not necessarily mean the vision of an open design environment has been achieved. Certainly, the general adoption of this standard will be a major milestone in the effort to create a totally interoperable environment, but while this database offers the fundamental infrastructure for design-side standards, widespread adoption still depends on several key functional requirements.

Interoperable Foundry Design Kits

One such requirement is a Pcell library, a critical part of every foundry physical design kit (PDK). Pcells are “parameterized” cells used in the design of analog and custom digital circuits that take the place of many fixed cells by allowing the substitution of different values for specified dimensional variables (parameters). A single Pcell for an NMOS transistor, for example, can be substituted for an almost infinite number of device sizes  by changing the gate length parameter for a particular placement or “instance.” In addition, advanced capabilities associated with Pcells offer the ability to substitute formulas or functions for some variables so necessary relationships are maintained (e.g., automatically extending the poly endcap when the diffusion width varies). Furthermore, some Pcells can automatically adapt to inputs from simulation to derive the appropriate values based upon specified conditions. Until all the major components, libraries and functionalities are interoperable, the value of an open database alone is very limited, especially for analog and custom digital design.

Analog circuits are designed in schematic form using symbols that correspond to specific devices, with specified values. Today, layout designers know advanced layout tools will automatically generate correctly sized design rule check (DRC) layout (i.e., the correct Pcell layout free of design rule violations with the correct value for the design) and merge multiple devices for space efficiency without ever having to “draw” a single shape. Connections for the cells are specified in the schematic, and routers offer various alternatives for routing (wiring) them correctly within the layout tool environment, either manually or automatically. Virtually, all high-end layout tools have Pcell mechanisms that work in this fashion. The problem is most Pcells in use today have been written in the proprietary language of a single vendor. Offering Pcells in additional languages for other vendors and assuring that they act exactly as the original version is a redundant and burdensome task for foundries, customers and EDA vendors alike. Customers are limited by economics to using only tools supported in the foundry PDK, regardless of their own preferences. In Figure 2, a customer using three foundries and tools from three EDA vendors might need as many as nine PDKs for each technology node. With an open standard, that number could be reduced to three PDKs, and with advanced tools, the user might even share a single Pcell library.

People Working Together

For reasons previously stated, a number of EDA companies in the custom and analog design space were highly motivated to work together to create an open environment.   Anyone who has been part of a multi-company collaboration knows a majority of these initiatives fail, and the most common outputs are PowerPoint slides, “vanilla” solutions and many promises. By this measure, the IPL Initiative has been working at warp speed. The fact that this ad-hoc, unfunded group could accomplish so much in such a short period of time is the strongest argument that the time for collaboration on this issue has arrived. Mutual interest and mutual benefit are the fuel for collaborative success, and the results from this initiative say a great deal about the potential benefits. For the first time, an IC designer will be able to use the same Pcell libraries in tools from multiple vendors.  Interoperable Pcells with advanced Pcell functionality will go a long way toward creating the long-awaited open PDKs for foundries that work seamlessly in all EDA tools. With a little effort and advanced capabilities, customers can realize the dream of creating Pcells that are “portable” among multiple foundries – at least within a specific technology node.

Tools Working Together

In the fall of 2007, a schematic created in one tool from one vendor using standard symbols and saved in an open database was opened in another vendor’s tools, modified and passed to the tool of a third vendor, where changes were evident and connectivity still intact. A layout created from the schematic using the Initiative’s interoperable Pcell Library was opened in one tool, where some Pcell parameters were changed and a couple of nodes routed (demonstrating continuing connectivity) while creating intentional DRC violations. DRCs were run using another vendor’s tool, and error flags were displayed with the layout in the tool of another. The layout tool repaired the errors, more routing was added and DRCs were run by another vendor’s tool to show the layout was now free of violations. At no time was the original data converted to another format such as GDSII. While this is a major achievement, the big winners will soon be foundries and their fabless customers who will be able to use the same Pcell libraries in tools from multiple vendors. For the first time, customers will benefit from best-in-class design toolsets, knowing that foundry-approved design kits will work seamlessly throughout their design flow.

Why is this a remarkable achievement? After all, customers expect tools to work this way! The fact that this is at all extraordinary is one reason many large semiconductor companies continue to use internally developed EDA tools. In the computer world, customers expect hardware and software to work together seamlessly, using agreed-upon communication protocols over seamless networks that use standard plugs and connectors. To be accepted in the marketplace, a vendor’s tools must interoperate seamlessly. A vendor deviates from standards at its peril, and will be left behind if a more compatible alternative comes into the market, as they always do. It is a competitive advantage to interoperate because it is what every customer desires. Why should EDA be any different?

Summary

When running on an open database, open Pcells and open Pcell features promise to level the playing field for innovative EDA start-ups and top EDA vendors. Once the cost and effort of developing a database are eliminated and the barriers to interoperability are removed, new ideas and products will flourish. Already, there are numerous EDA start-ups and veterans working to increase the levels of analog automation and overall design productivity. A level playing field will encourage bright entrepreneurs, university researchers and others to create and implement new ideas. Time and time again, increased competition has shown that incumbent products must evolve to survive. Lack of competition in the design chain supports the status quo.  Those collaborating on the open environment possess the confidence that competition will improve their products as much as it does their competitors, and believe they have an obligation to innovate andcollaborate to keep pace with customer needs.

Design is no longer isolated from manufacturing. Bitter product competitors are collaborating to develop advanced processes because they cannot afford to go it alone. In the same way, the EDA supply chain can’t afford to not collaborate. Increasingly, customers are demanding interoperability. Failure to collaborate cedes the advantage to the next competitor or group willing to work together to create something better.

The design-side supply chain is no different than any other component of the semiconductor supply chain.“The way we have always done it” is no longer good enough, and collaboration is becoming a priority. The progress of the Initiative outlined above shows that it is possible to achieve tangible and meaningful results when sufficiently motivated. When people work together, they can work wonders.

About the Author

Richard Morse currently serves as director of marketing for Silicon Canvas. Morse has more than 30 years experience in the semiconductor industry in a career that includes photomasks, semiconductors and, more recently, design for manufacturability (DFM) and IC design software. He spent over 14 years directing tapeout operations at Cirrus Logic, as it became the first billion-dollar fabless semiconductor company. He has worked at four start-ups and founded Design- to-Wafer Services (D2W), the industrys first dedicated tapeout services company, in 1999. Morse has been a lecturer, author and session chair on mask data preparation and DFM at SPIE conferences.