Addressing the power-aware debug challenge
Bindesh Patel, SpringSoft Inc.
When it comes to design verification, one fact is undeniable: as the biggest contributor to design cycle time, it remains a key pain point in the development of today's sophisticated SoCs. As if that weren't a difficult enough challenge to contend with, today's engineers must also now confront concerns over power and its impact on the overall design, verification and implementation process. One reason for the concern is the growing number of applications with their ever increasing functionality that demands low-power operation to support a longer battery life. Increasing power density, driven by higher clock speeds and shrinking process geometries, is another reason for concern over power. Just as critical, is the fact that today's SoCs are often composed of multiple blocks running multiple applications with varying power requirements.