Debugging and analysis with SystemVerilog test bench

Some minor additions to OVM libraries can open a new world of visibility for design verifiers.

By Bindesh Patel and Rex Chen, SpringSoft -- EDN, 2/4/2010

The verification component of SystemVerilog has dominated the rapid adoption of the language. The new verification syntax in the language allows for dramatic productivity gains in the verification cycle, which itself is now the major portion of the entire design and verification cycle. However, the debugging process of such environments brings about additional complexities. First, unlike with RTL (register-transfer-level) logic, no callback-driven "dumpvars"-type, dump-everything schemes exist for the object-oriented, software-like SystemVerilog verification constructs. Using these capabilities, engineers have access to the entire history of events that occur during a simulation. Once available, this data can drive basic capabilities, such as waveforms and overlay of the trace data onto familiar source code and schematic views, and automation, such as multicycle tracing to the root cause with one command or mouse click.

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