Help - All of my simulations are passing!
By George Bakewell
EDA DesignLine
This statement of anguish - rarely uttered in the annals of functional verification history - is certainly absurd on its face. After all, verification engineers continually strive for the holy grail of clean regressions, toiling day-after-day to cleanse the system of failing tests on their way to tape-out nirvana. But pause and consider for a moment a world in which passing tests are not an indicator that all is well, but rather a warning flag that not enough functionality is being tested, vital checks that confirm proper operation of the design are missing, or - worse yet - problems in the verification infrastructure are masking test failures and hiding RTL bugs merrily making their way to fabrication. Such musings might lead one to ask, who's verifying the verification environment?
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