Visibility Enhancement Technology Confronts the Visibility Issue with Full-Chip Simulation

by Martin Rowe, Technical Manager, SpringSoft, Inc.

When it comes to system-on-chip verification, two trends have become painfully obvious: it is expensive and it takes too long. Consider, for example, that the most expensive parts of today’s SoC design flow are the tasks where the engineer must engage in direct manual effort or expend energy making decisions. In the case of verification, far too much time and money are wasted on tasks that don’t add value, such as trying to figure out how supposedly-correct intellectual property (IP) is actually working, debugging “dumb” errors or deciding what signals to record in any given simulation run. While improved design tools and methodologies, coupled with higher levels of abstraction, have made some headway in shortening design and verification times, the time required to determine the root cause of problems found in large, long simulations is growing.

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