Schematic-Driven Layout Automation
Circuit designs continue to get larger and more complicated. Custom layout, like most steps in the IC design flow, has become more tedious and time consuming. Designers are always looking for better tools to automate the process and help them become more productive. Schematic-driven layout (SDL) is a design methodology that assists designers with the physical implementation of circuits, by providing automation and continuity between logic and layout. SDL relies on device generation technology for automation of the creation of physical layout from schematic elements.
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Laker Custom Layout Parameterized Devices
A parameterized device (Pdevice) is used in the design of analog and custom digital integrated circuits to take the place of many fixed cells by allowing the substitution of different values for specified dimensional variables (parameters). Pdevices not only save an enormous amount of manual layout time; they also facilitate additional levels of automation that compound their inherent productivity. Today the term “parameterized devices” and “PCells” are virtually synonymous. Each PCell is a software script (a sequence of commands) used to define physical layout based on a prescribed set of parameters. Most PCells are written in proprietary scripting languages and can only be used with tools from the same vendor. The Laker Custom Layout System supports four types of Pdevices: SpringSoft’s patented Magic Cells (MCell™), User-Defined Devices (UDD), Tcl PCells and soon, PyCells™. All of the Laker Pdevices are readable as layout data in GDSII by other EDA tools without any proprietary evaluation engine. PyCells are completely interchangeable among OpenAccess-based tools. Although MCells are parameterized devices, they are not PCells. They provide a more advanced, flexible and dynamic way of generating optimized device layout.
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Laker PDK
Designing a semiconductor chip requires a set of physical and electrical design rules that specify the minimum manufacturing requirements and that describe how the design will function when those rules are met. In order to convey the manufacturing requirements and device performance to integrated circuit (IC) designers and to assist them in implementing them correctly, the electronic design automation (EDA) community developed the concept of Process Design Kits (PDKs) working with contract wafer manufacturers (pure-play foundries) like TSMC, UMC, SMIC and Chartered Semiconductor Manufacturing. The “process” in “PDK” refers to the specific semiconductor manufacturing technology for which a design kit has been created. PDKs are seen throughout the industry as an important part of the IC development ecosystem, which when coupled with IC design and verification software from EDA tool providers, provide the basic design environment and all the necessary technical data to create an integrated circuit. They play a vital role in maximizing design productivity, and provide timely access to the latest, most accurate information for chip manufacturing technologies. In this way, PDKs enable chip designers to achieve shorter time to market and first-pass silicon success of designs that function as intended, offer less risk and yield more predictable results.
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