Custom IC Design Technical Papers
Digital Place and Route in a Custom Design Environment
There is a category of high-end integrated circuits (ICs) – often referred to as "analog-on-top" since the top level description is a SPICE netlist – that predominantly comprise analog circuitry augmented with blocks of digital functionality. Until recently, these digital blocks were relatively small, each typically containing only a few tens, hundreds, or (sometimes) thousands of logic cells. Such blocks were often handcrafted by the analog designers using traditional custom design capture and layout technologies.
PCell Caching in OpenAccess
In computer programs, caching is used to store the output from commonly used functions on the disk so that, when executing a repeated instruction, the results may be obtained more quickly without having to reprocess the request. This same mechanism can be used to speed up the display of parameterized cells (PCells) in custom IC design. Some Electronic Design Automation (EDA) tools cache PCells automatically for performance reasons; some require additional licenses; and others offer no caching at all. In addition to the performance benefits, PCell caching can be used to make tool-specific PCells visible in other tools in the design flow.
When People Work Together, IC Design Tools Work Together
In late 2006, five Electronic Design Automation (EDA) software companies came together and agreed to collaborate on the creation and distribution of an interoperable Pcell library (IPL) and an open infrastructure for its use. This proof-of-concept Pcell library was developed and released in less than six months, and in less than a year, demonstrated live at the fall 2007 Si2 OpenAccess conference operating in eight different tools from five different EDA companies. The success of this unlikely gathering of competitors shows that the benefits of collaboration extend all the way into integrated circuit (IC) design tool supply chain.
Controllable Automation and Interoperability Standards
Layout for large digital integrated circuit (IC) designs is generally created using highly automated place-and-route (APR) tools. Although there are tradeoffs for using APR instead of custom layout, the speed and confidence offered by APR far out weigh the compromises in area or performance for most designs. But, designs that require the utmost in performance and/or the smallest possible area are still done “by hand” using custom IC layout methodologies. In the next generation of custom chips, complicated rules, tight time-to-market schedules, and the sheer size and complexity of designs are making full-custom digital blocks increasingly difficult to implement. Fully-automated APR flows cannot offer the kind of interactive control of the layout and routing that is necessary. Designers need a highly-automated yet controllable full custom digital IC design flow that optimizes performance, speed, and area.
Schematic-Driven Layout Automation
Circuit designs continue to get larger and more complicated. As a rule of thumb, layout productivity must double with every new process node in order to keep pace with Moore’s law. For digital implementation, the automatic place and route (AP&R) tools have done a good job of keeping pace. However, productivity gains are harder to achieve for custom IC design. By its nature, custom (transistor-level) design still tends to be done largely by hand by circuit experts. Even when the analog content of today’s SOCs is relatively small, it is not uncommon for the analog portion of the chip to become the gating item in the tapeout schedule.
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