Designing a semiconductor chip requires
a set of physical and electrical design rules that specify the minimum
manufacturing requirements and that describe how the design will
function when those rules are met. In order to convey the manufacturing
requirements and device performance to integrated circuit (IC)
designers and to assist them in implementing them correctly, the
electronic design automation (EDA) community developed the concept of
Process Design Kits (PDKs) working with contract wafer manufacturers
(pure-play foundries) like TSMC, UMC, SMIC and Chartered Semiconductor
Manufacturing. The “process” in “PDK” refers to the specific
semiconductor manufacturing technology for which a design kit has been
created. PDKs contain a collection of documents
and design infrastructure elements. They are generally associated with
custom design, especially analog. But, even standard cell library
developers are custom designers and will use many of the PDK elements.
In the long list of PDK contents (refer to GSA PDK checklist),
the key elements include: manufacturing rules; simulation models of
various kinds, runset files for tools that verify physical and
electrical design rules; and schematic symbol libraries, parameterized
cells (generically called “PCells”), a layer-map and technology
(“tech”) file for layout tools. PDKs are developed specifically for
each manufacturer, wafer process flow, and technology node. In
addition, most of the design infrastructure elements are necessarily
specific to each supported EDA tool. The individual components of PDKs
are created by EDA vendors and/or the foundries themselves. Today, all
major providers of custom IC design tools today, including SpringSoft,
Cadence and Mentor Graphics supply PDKs, often collaborating directly
with the foundries on joint development and validation. The Laker™ Custom Layout System from
SpringSoft offers specialized solutions for analog, mixed-signal,
memory, and custom digital IC design that address key pain points in
the layout process. The Laker layout system provides an intuitive
methodology and controllable automation that enable chip designers to
quickly achieve superior layout results with less effort than
traditional methods. The Laker layout system removes many tedious
manual processes while still providing complete control over the design
implementation with production-proven schematic-driven layout and
rule-driven automation. The Laker layout system is used today by more
than 300 companies worldwide, including 7 of the top 10 semiconductor
companies, for designs down to 45 nanometers (nm). For more information
about the Laker products, visit: http://www.springsoft.com/product/.Introduction
What is a PDK?
Laker PDK
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