Schematic-Driven Layout Automation

Introduction

Circuit designs continue to get larger and more complicated. As a rule of thumb, layout productivity must double with every new process node in order to keep pace with Moore’s law.  For digital implementation, the automatic place and route (AP&R) tools have done a good job of keeping pace. However, productivity gains are harder to achieve for custom IC design. By its nature, custom (transistor-level) design still tends to be done largely by hand by circuit experts. Even when the analog content of today’s SOCs is relatively small, it is not uncommon for the analog portion of the chip to become the gating item in the tapeout schedule.

Schematic-driven layout (SDL) is a design methodology that assists designers with the physical implementation of circuits while maintaining the continuity and parameters specified in the schematic. The Laker™ Custom Layout Automation System has a schematic-driven layout flow which addresses the issues above with a smooth, intuitive, drag-and-drop flow that speeds time to layout in several ways.

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