Verification Enhancement Technical Papers
Customization and Reuse of Interoperable Verdi Applications
Design knowledge platform enables rapid creation of custom applications
that leverage correlated design and verification data
» more
Speeding Verification of FPGA-Based Prototype Boards with the ProtoLink Probe Visualizer
It is well-accepted that code review is desirable
to ensure the quality of RTL designs. However,
from a management perspective, the lack of
specific targets beyond coding guidelines often
makes it difficult to gain uniform participation,
and measure results. Furthermore, traditional
code review is incomplete in that it only considers
the static RTL, rather than examining it in the
full context of how the code is exercised in the test
environment.
» more
Functional Review using SpringSoft Verdi Automatic Debug and NextOp BugScope Assertion Synthesis
It is well-accepted that code review is desirable
to ensure the quality of RTL designs. However,
from a management perspective, the lack of
specific targets beyond coding guidelines often
makes it difficult to gain uniform participation,
and measure results. Furthermore, traditional
code review is incomplete in that it only considers
the static RTL, rather than examining it in the
full context of how the code is exercised in the test
environment.
» more
Introducing Functional Qualification
Functional verification consumes a significant portion of the time and resources devoted to the typical design project. As chips continue to grow in size and complexity, designers must increasingly rely on a dedicated verification team to ensure that systems fully meet their specifications.
Verification engineers have at their disposal a set of dedicated tools and methodologies for verification automation and quality improvement. In spite of this, functional logic errors remain a significant cause of project delays and re-spins.
» more
Challenges and Requirements for Power-Aware Debug
Traditionally, area and timing have been the major issues faced by Integrated Circuit (IC) designers. Now, power has also emerged as a major concern for three reasons. First, low power is favored by numerous end-applications, such as cellular phones, hand-held gaming devices, and portable media players. Second, there is an increase in power density due to higher clock speeds and shrinking process geometries control. Last but not least, most system-on-chip (SoC) designs are composed of different blocks running multiple applications with varying power requirements.
» more
< Previous Showing 1 - 5 of 11 | Page 1 of 3 | next »
