Introducing Functional Qualification
Functional verification consumes a significant portion of the time and resources devoted to the typical design project. As chips continue to grow in size and complexity, designers must increasingly rely on a dedicated verification team to ensure that systems fully meet their specifications.
Verification engineers have at their disposal a set of dedicated tools and methodologies for verification automation and quality improvement. In spite of this, functional logic errors remain a significant cause of project delays and re-spins.
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Challenges and Requirements for Power-Aware Debug
Traditionally, area and timing have been the major issues faced by Integrated Circuit (IC) designers. Now, power has also emerged as a major concern for three reasons. First, low power is favored by numerous end-applications, such as cellular phones, hand-held gaming devices, and portable media players. Second, there is an increase in power density due to higher clock speeds and shrinking process geometries control. Last but not least, most system-on-chip (SoC) designs are composed of different blocks running multiple applications with varying power requirements.
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SystemVerilog Testbench Debug & Analysis
The verification component of SystemVerilog brings high-level programming capability to design and verification teams. In the past, many teams utilized a C/C++ testbench, native or SystemC-based, to drive a more efficient, realistic test of the design. SystemVerilog brings structure to this process by providing a standard object-oriented language with which to do the same. Tools can now be developed to support a more standard, structured process in a way that is not intimidating to the engineers who previously coded in Verilog or VHDL and are not familiar with a language such as C++.
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Advanced Techniques for RTL Debugging - Presented at DAC
Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) source. This process is helpful in locating errors but does little to help designers reason about the how and why. Designers usually have to build a mental image of how data is propagated and used over the simulation run. As designs get more and more complex, there is a need to facilitate this reasoning process, and automate the debugging. In this paper, we present innovative debug techniques to address this shortage in adequate facilities for reasoning about behavior, and debugging errors. Our approach delivers significant technology advances in RTL debugging; it is the first comprehensive and methodical approach of its kind that extracts, analyzes, traces, explores, and queries a design’s multi-cycle temporal behavior. We show how our automatic tracing scheme can shorten debugging time by orders of magnitude for unfamiliar designs. We also demonstrate how the advanced debug techniques reduce the number of regression iterations.
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SpringSoft Debug Technology White Paper
As chip size and complexity increases, design verification becomes an increasingly costly and time-consuming part of product development. Products such as simulators, formal verification tools, and hardware emulators and accelerators automate the process of detecting design defects, and have accelerated the rate at which these "bugs" can be found. However, the debug part of the process has remained a bottleneck, because it requires an engineer with knowledge of the design to spend time trying to figure out how the design is supposed to work and understand why it doesn’t function as intended.
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