Shrinking silicon geometries enable
larger SoC-type designs in terms of raw gate size, and many of today’s
applications take advantage of this trend. An important point that is
often missed is the accompanying growth in verification complexity.
Indeed, the verification task for a design that is twice as big is
actually more than doubled. The verification team has to deal with a
bigger state-space and the application, which is what the verification
environment attempts to mimic, gets much “bigger”. Simply building faster tools like
simulators will not solve this problem. Rather, it requires
capabilities and associated methodologies that make it easier to set up
complex verification environments – environments that in the end ensure
that the application on the chip works as expected. Fortunately,
SystemVerilog provides a compelling advantage in addressing the
complexity challenge - not simply as a new language for describing
complex structures, but as a platform for enabling advanced
methodologies and automation. Each of the three key aspects of
SystemVerilog has a significant role. The synthesizable design
constructs that have been added to SystemVerilog make it possible for
designers to code at a higher level of abstraction, often mapping more
accurately to the function they are designing and the way they think
about it. The new assertions capability allows users to very concisely
describe a behavior that needs to be checked. But it is the
verification aspect that provides the biggest bang for the buck, as
evidenced by its rapid adoption. The verification component of
SystemVerilog brings high-level programming capability to design and
verification teams. In the past, many teams utilized a C/C++
testbench, native or SystemC-based, to drive a more efficient,
realistic test of the design. SystemVerilog brings structure to this
process by providing a standard object-oriented language with which to
do the same. Tools can now be developed to support a more standard,
structured process in a way that is not intimidating to the engineers
who previously coded in Verilog or VHDL and are not familiar with a
language such as C++. The SystemVerilog testbench (SVTB)
language still resembles Verilog code for the most part. Additionally,
it includes built-in support for functionality that is commonly needed
during verification, such as constrained randomization and coverage
monitoring. The relatively simple notion of constrained randomization
allows engineers to develop sophisticated test scenarios with very few
lines of code. It is also a natural progression for the object-oriented
model to spur standard class libraries and related OVM (Open
Verification Methodology) and VMM (Verification Methodology Manual)
methodologies, both of which enable engineers to create modular,
reusable verification environments in which components communicate with
each other via standard transaction-level modeling interfaces. It also
enables intra- and inter-company reuse through a common methodology and
classes for virtual sequences and block-to-system reuse. This reuse can
be extended to off-the-shelf verification IP components that can be
used to verify specific functionality such as bus protocols like USB.
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