Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) source. This process is helpful in locating errors but does little to help designers reason about the how and why.  Designers usually have to build a mental image of how data is propagated and used over the simulation run. As designs get more and more complex, there is a need to facilitate this reasoning process, and automate the debugging. In this paper, we present innovative debug techniques to address this shortage in adequate facilities for reasoning about behavior, and debugging errors. Our approach delivers significant technology advances in RTL debugging; it is the first comprehensive and methodical approach of its kind that extracts, analyzes, traces, explores, and queries a designs multi-cycle temporal behavior. We show how our automatic tracing scheme can shorten debugging time by orders of magnitude for unfamiliar designs. We also demonstrate how the advanced debug techniques reduce the number of regression iterations.

1.      INTRODUCTION

Debugging is generally a major endeavor for the designer with large and complex designs since these are typically:

·     Heterogeneous: composed of varied components possibly intellectual property (IP) blocks from several (best-in-class) providers; 

·     Mixed: made up of portions described at different abstraction levels - behavioral as well as structural; and

·     Diverse: composed of multiple computation domains that model real world interaction such as sensors, transducers, digital-to-analog and/or analog-to-digital converters.

The stimulus and response data used to exercise and observe design behavior is also a large and varied data set. Manipulating, studying, and analyzing this data and its correlation with expected or desired behavior, and the designs implementation (i.e., actual) behavior is a horrendous undertaking. The process of debugging involves locating the logic that is associated with an error, isolating the pertinent cause and effect relationships, and understanding exactly how the design is supposed to behave and why it is not behaving that way as shown in Figure 1. Debug, with its demands for time and energy from expert designers, is quickly becoming the bottleneck in the verification process for todays complex system-on-chip (SoC) designs.

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