Introduction
Functional verification consumes a significant portion of the time and resources devoted to the typical design project. As chips continue to grow in size and complexity, designers must increasingly rely on a dedicated verification team to ensure that systems fully meet their specifications.
Verification engineers have at their disposal a set of dedicated tools and methodologies for verification automation and quality improvement. In spite of this, functional logic errors remain a significant cause of project delays and re-spins. A key reson is that two important aspects of verification environment quality - the ability to propogate the effect of a bug to an abservable point and the ability to observe the faulty effect and thus detect the bug - cannot be analyzed or measured. Existing methods, such as functional coverage and code coverage, largly ignore these two aspects, allowing functional errors to escape the verification process despite excellent coverage scores. Existing tools are simply unable to assess the overall quality of simulation-based functional verification environments.
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