Speeding Verification of FPGA-Based Prototype Boards with the ProtoLink Probe Visualizer

Real-time design visibility and RTL debug of off-the-shelf and custom boards accelerate prototype verification and enable early SoC system validation

System-on-chip (SoC) designs continue to increase in size and complexity. At the same time, market windows are shrinking and today's electronic markets are extremely sensitive to time-to-market pressures. All of this is putting tremendous demands on SoC design and verification teams. Indeed, it is now widely accepted that verification accounts for around 70 percent of the total SoC development cycle. Therefore, anything that decreases verification costs, speeds verification runs, and facilitates verification earlier in the development cycle is of extreme interest.

Many companies are moving to a FPGA-based prototyping approach for system-level validation of key design modules or entire systems with application software to take advantage of performance and lower cost benefits. However, prototype deployment is often delayed and limited to late in the development cycle because they are inherently difficult to setup and lack the visibility needed to adequately debug designs.

SpringSoft’s ProtoLink^™ Probe Visualizer introduces an innovative and affordable software-driven method for dramatically increasing design visibility and simplifying the debug of “off-the-shelf” and custom-designed FPGA prototype boards. It combines patented interconnect innovations and specialized software automation with the industry-leading Verdi^™ HDL debug platform to shorten the verification cycle and maximize return on investment with faster, earlier deployment to SoC design and verification teams.

System-on-chip (SoC) designs continue to increase in size and complexity. At the same time, market windows are shrinking and today's electronic markets are extremely sensitive to time-to-market pressures. All of this is putting tremendous demands on SoC design and verification teams. Indeed, it is now widely accepted that verification accounts for around 70 percent of the total SoC development cycle. Therefore, anything that decreases verification costs, speeds verification runs, and facilitates verification earlier in the development cycle is of extreme interest.

Many companies are moving to a FPGA-based prototyping approach for system-level validation of key design modules or entire systems with application software to take advantage of performance and lower cost benefits. However, prototype deployment is often delayed and limited to late in the development cycle because they are inherently difficult to setup and lack the visibility needed to adequately debug designs.

SpringSoft’s ProtoLink^™ Probe Visualizer introduces an innovative and affordable software-driven method for dramatically increasing design visibility and simplifying the debug of “off-the-shelf” and custom-designed FPGA prototype boards. It combines patented interconnect innovations and specialized software automation with the industry-leading Verdi^™ HDL debug platform to shorten the verification cycle and maximize return on investment with faster, earlier deployment to SoC design and verification teams.

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