Executive Summary

Software simulation is the primary method used to verify logic in integrated circuit (IC) designs. When simulation discovers logic errors through unexpected logical behavior, users must trace the causes. This tracing requires that logic values be recorded during simulation. For large designs, recording these values adds enormous overhead to the simulation process. This causes users to adopt a variety of costly strategies for reducing this overhead. New Visibility Enhancement technology enables methodologies that reduce the need for this manual effort and improve the overall productivity of logic verification with simulation. This technology identifies a minimal subset of signals required for full visibility and automatically expands the data for other signals from this recorded subset during debug.

Simulation, Visibility, and Debug

Software-based simulation is the primary method used to verify IC designs.  According to Gartner-Dataquest, over 160,000 simulation licenses are in use for verifying ASIC and FPGA designs[i].  Instrumental to this widespread use is a vast investment in user-created scripts and regression suites that leverage the flexibility of the venerable simulator.  Continued performance and capacity improvements in simulation technology, as well as new functionality including assertions and high-level abstractions such as transactions, have extended the usefulness of simulation and preserved the infrastructure investment.  As the size of ICs has exploded, the time required to thoroughly verify them with simulation has risen dramatically. This increase is especially acute when the values of signals must be recorded in order to facilitate visibility into understanding the designs behavior.

 

Understanding design behavior is one of the most difficult challenges in IC verification.  The process of understanding the behavior of a design is known as “debug” or “debugging” and is an interactive process separate from simulation[ii].  Debug requires recording the signal values generated during simulation. High signal visibility is critical to effective debugging.   

 

Design complexity, as measured by the number of signal value combinations, grows faster than design gate counts Consider a design that currently contains N gates, the next generation will contain 2ŸN gates, the lower bound number of signals will be 2ŸN, and the corresponding minimum number of signal value combinations will be 2(2N) or 4x more than the current design (Figure 1).  With the doubling of design sizes every 24 months[iii] continues, the overhead of gathering the signal data required for visibility will continue to increase significantly. 

 

 

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