Verification Enhancement Technical Papers
SystemVerilog Testbench Debug & Analysis
The verification component of SystemVerilog brings high-level programming capability to design and verification teams. In the past, many teams utilized a C/C++ testbench, native or SystemC-based, to drive a more efficient, realistic test of the design. SystemVerilog brings structure to this process by providing a standard object-oriented language with which to do the same. Tools can now be developed to support a more standard, structured process in a way that is not intimidating to the engineers who previously coded in Verilog or VHDL and are not familiar with a language such as C++.
Advanced Techniques for RTL Debugging - Presented at DAC
Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) source. This process is helpful in locating errors but does little to help designers reason about the how and why. Designers usually have to build a mental image of how data is propagated and used over the simulation run. As designs get more and more complex, there is a need to facilitate this reasoning process, and automate the debugging. In this paper, we present innovative debug techniques to address this shortage in adequate facilities for reasoning about behavior, and debugging errors. Our approach delivers significant technology advances in RTL debugging; it is the first comprehensive and methodical approach of its kind that extracts, analyzes, traces, explores, and queries a design’s multi-cycle temporal behavior. We show how our automatic tracing scheme can shorten debugging time by orders of magnitude for unfamiliar designs. We also demonstrate how the advanced debug techniques reduce the number of regression iterations.
Assertion-Based Hardware Debugging - presented at DVCon
Today’s increasing design complexity requires innovation in both debug automation, and user interaction. We present here a novel query-based method that uses assertions as queries to assist in the domain of hardware debugging. Our approach is generally applicable to hardware debug, and is independent of the particulars of the input design or the assertion description language. We show how assertions drive the debugging process in order to diagnose the cause of the faulty behavior through the unique techniques of trace slicing, and trace dicing. We also present here a new visualization and user interaction technique specifically designed for complex systems with numerous component interactions and abundant control flows. The visualization approach leverages design and assertion spans to present the debugging information to the user in a refined detail of abstraction and permit adequate interaction. An experimental debugging system incorporating assertion-based debug guidance has been implemented. Experimental results for productivity enhancements from a case study will be presented.
Visibility Enhancement for Silicon Debug - Presented at DAC 2006
Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require the instrumentation of on-chip logic for extracting the internal register data from in situ silicon. Unfortunately, lack of visibility of the combinational network values impedes the ability to functionally debug the silicon part. Visibility enhancement techniques enable the virtual observation of combinational nodes with minimal computational overhead. These techniques also cover the register selection analysis for DFD and multi-level design abstraction correlation for viewing values at the register transfer level (RTL). Experimental results show that visibility enhancement techniques can leverage a small amount of extracted data to provide a high amount of computed combinational signal data. Visibility enhancement provides the needed connection between data obtained from the DFD logic and HDL simulation-related debug systems.
Visibility Enhancement Technology for Simulation
Although new tools, improved methodologies and higher levels of abstraction are shortening design and verification times, the time required to (and difficulty associated with) determining the root cause of problems found in large, long simulations is growing. A key factor stretching debug times for full-chip verification applications is the impact of observing signal values. Effective debug requires the engineer to observe and record signal values over time so that the causes of design behavior can be investigated and understood. But observing signal values impacts design and verification. It takes time to dump and record the signal values that must be observed. As a result, simulation run-times stretch. For large chips, the sheer quantity of data limits what can be observed, leading to methodologies that require multiple simulation runs to isolate the cause of a given problem if "the right signals" aren’t captured the first time around. Visibility enhancement provides the engineer a way to optimize visibility by making tradeoffs between impact and observability. With lots of impact, it is easy to see everything. With no impact, nothing can be observed. The trick is to find a way to minimize impact while achieving full visibility - or at least enough visibility to debug the problem.